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torvaldstorvalds
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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Ingo Molnar: "Mostly tooling fixes, plus two uncore-PMU fixes, an uprobes fix, a perf-cgroups fix and an AUX events fix" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/intel/uncore: Add enable_box for client MSR uncore perf/x86/intel/uncore: Fix uncore num_counters uprobes/x86: Fix RIP-relative handling of EVEX-encoded instructions perf/core: Set cgroup in CPU contexts for new cgroup events perf/core: Fix sideband list-iteration vs. event ordering NULL pointer deference crash perf probe ppc64le: Fix probe location when using DWARF perf probe: Add function to post process kernel trace events tools: Sync cpufeatures headers with the kernel toops: Sync tools/include/uapi/linux/bpf.h with the kernel tools: Sync cpufeatures.h and vmx.h with the kernel perf probe: Support signedness casting perf stat: Avoid skew when reading events perf probe: Fix module name matching perf probe: Adjust map->reloc offset when finding kernel symbol from map perf hists: Trim libtraceevent trace_seq buffers perf script: Add 'bpf-output' field to usage message
2 parents 1f8083c + 95f3be7 commit ad83242

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19 files changed

+298
-93
lines changed

19 files changed

+298
-93
lines changed

‎arch/x86/events/intel/uncore_snb.c

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,12 @@ static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
100100
}
101101
}
102102

103+
static void snb_uncore_msr_enable_box(struct intel_uncore_box *box)
104+
{
105+
wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
106+
SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
107+
}
108+
103109
static void snb_uncore_msr_exit_box(struct intel_uncore_box *box)
104110
{
105111
if (box->pmu->pmu_idx == 0)
@@ -127,6 +133,7 @@ static struct attribute_group snb_uncore_format_group = {
127133

128134
static struct intel_uncore_ops snb_uncore_msr_ops = {
129135
.init_box = snb_uncore_msr_init_box,
136+
.enable_box = snb_uncore_msr_enable_box,
130137
.exit_box = snb_uncore_msr_exit_box,
131138
.disable_event = snb_uncore_msr_disable_event,
132139
.enable_event = snb_uncore_msr_enable_event,
@@ -192,6 +199,12 @@ static void skl_uncore_msr_init_box(struct intel_uncore_box *box)
192199
}
193200
}
194201

202+
static void skl_uncore_msr_enable_box(struct intel_uncore_box *box)
203+
{
204+
wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
205+
SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);
206+
}
207+
195208
static void skl_uncore_msr_exit_box(struct intel_uncore_box *box)
196209
{
197210
if (box->pmu->pmu_idx == 0)
@@ -200,6 +213,7 @@ static void skl_uncore_msr_exit_box(struct intel_uncore_box *box)
200213

201214
static struct intel_uncore_ops skl_uncore_msr_ops = {
202215
.init_box = skl_uncore_msr_init_box,
216+
.enable_box = skl_uncore_msr_enable_box,
203217
.exit_box = skl_uncore_msr_exit_box,
204218
.disable_event = snb_uncore_msr_disable_event,
205219
.enable_event = snb_uncore_msr_enable_event,

‎arch/x86/events/intel/uncore_snbep.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2626,7 +2626,7 @@ void hswep_uncore_cpu_init(void)
26262626

26272627
static struct intel_uncore_type hswep_uncore_ha = {
26282628
.name = "ha",
2629-
.num_counters = 5,
2629+
.num_counters = 4,
26302630
.num_boxes = 2,
26312631
.perf_ctr_bits = 48,
26322632
SNBEP_UNCORE_PCI_COMMON_INIT(),
@@ -2645,7 +2645,7 @@ static struct uncore_event_desc hswep_uncore_imc_events[] = {
26452645

26462646
static struct intel_uncore_type hswep_uncore_imc = {
26472647
.name = "imc",
2648-
.num_counters = 5,
2648+
.num_counters = 4,
26492649
.num_boxes = 8,
26502650
.perf_ctr_bits = 48,
26512651
.fixed_ctr_bits = 48,
@@ -2691,7 +2691,7 @@ static struct intel_uncore_type hswep_uncore_irp = {
26912691

26922692
static struct intel_uncore_type hswep_uncore_qpi = {
26932693
.name = "qpi",
2694-
.num_counters = 5,
2694+
.num_counters = 4,
26952695
.num_boxes = 3,
26962696
.perf_ctr_bits = 48,
26972697
.perf_ctr = SNBEP_PCI_PMON_CTR0,
@@ -2773,7 +2773,7 @@ static struct event_constraint hswep_uncore_r3qpi_constraints[] = {
27732773

27742774
static struct intel_uncore_type hswep_uncore_r3qpi = {
27752775
.name = "r3qpi",
2776-
.num_counters = 4,
2776+
.num_counters = 3,
27772777
.num_boxes = 3,
27782778
.perf_ctr_bits = 44,
27792779
.constraints = hswep_uncore_r3qpi_constraints,
@@ -2972,7 +2972,7 @@ static struct intel_uncore_type bdx_uncore_ha = {
29722972

29732973
static struct intel_uncore_type bdx_uncore_imc = {
29742974
.name = "imc",
2975-
.num_counters = 5,
2975+
.num_counters = 4,
29762976
.num_boxes = 8,
29772977
.perf_ctr_bits = 48,
29782978
.fixed_ctr_bits = 48,

‎arch/x86/kernel/uprobes.c

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -357,20 +357,22 @@ static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
357357
*cursor &= 0xfe;
358358
}
359359
/*
360-
* Similar treatment for VEX3 prefix.
361-
* TODO: add XOP/EVEX treatment when insn decoder supports them
360+
* Similar treatment for VEX3/EVEX prefix.
361+
* TODO: add XOP treatment when insn decoder supports them
362362
*/
363-
if (insn->vex_prefix.nbytes == 3) {
363+
if (insn->vex_prefix.nbytes >= 3) {
364364
/*
365365
* vex2: c5 rvvvvLpp (has no b bit)
366366
* vex3/xop: c4/8f rxbmmmmm wvvvvLpp
367367
* evex: 62 rxbR00mm wvvvv1pp zllBVaaa
368-
* (evex will need setting of both b and x since
369-
* in non-sib encoding evex.x is 4th bit of MODRM.rm)
370-
* Setting VEX3.b (setting because it has inverted meaning):
368+
* Setting VEX3.b (setting because it has inverted meaning).
369+
* Setting EVEX.x since (in non-SIB encoding) EVEX.x
370+
* is the 4th bit of MODRM.rm, and needs the same treatment.
371+
* For VEX3-encoded insns, VEX3.x value has no effect in
372+
* non-SIB encoding, the change is superfluous but harmless.
371373
*/
372374
cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1;
373-
*cursor |= 0x20;
375+
*cursor |= 0x60;
374376
}
375377

376378
/*
@@ -415,12 +417,10 @@ static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
415417

416418
reg = MODRM_REG(insn); /* Fetch modrm.reg */
417419
reg2 = 0xff; /* Fetch vex.vvvv */
418-
if (insn->vex_prefix.nbytes == 2)
419-
reg2 = insn->vex_prefix.bytes[1];
420-
else if (insn->vex_prefix.nbytes == 3)
420+
if (insn->vex_prefix.nbytes)
421421
reg2 = insn->vex_prefix.bytes[2];
422422
/*
423-
* TODO: add XOP, EXEV vvvv reading.
423+
* TODO: add XOP vvvv reading.
424424
*
425425
* vex.vvvv field is in bits 6-3, bits are inverted.
426426
* But in 32-bit mode, high-order bit may be ignored.

‎include/linux/perf_event.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -743,7 +743,9 @@ struct perf_event_context {
743743
u64 parent_gen;
744744
u64 generation;
745745
int pin_count;
746+
#ifdef CONFIG_CGROUP_PERF
746747
int nr_cgroups; /* cgroup evts */
748+
#endif
747749
void *task_ctx_data; /* pmu specific data */
748750
struct rcu_head rcu_head;
749751
};
@@ -769,7 +771,9 @@ struct perf_cpu_context {
769771
unsigned int hrtimer_active;
770772

771773
struct pmu *unique_pmu;
774+
#ifdef CONFIG_CGROUP_PERF
772775
struct perf_cgroup *cgrp;
776+
#endif
773777
};
774778

775779
struct perf_output_handle {

‎kernel/events/core.c

Lines changed: 54 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -843,6 +843,32 @@ perf_cgroup_mark_enabled(struct perf_event *event,
843843
}
844844
}
845845
}
846+
847+
/*
848+
* Update cpuctx->cgrp so that it is set when first cgroup event is added and
849+
* cleared when last cgroup event is removed.
850+
*/
851+
static inline void
852+
list_update_cgroup_event(struct perf_event *event,
853+
struct perf_event_context *ctx, bool add)
854+
{
855+
struct perf_cpu_context *cpuctx;
856+
857+
if (!is_cgroup_event(event))
858+
return;
859+
860+
if (add && ctx->nr_cgroups++)
861+
return;
862+
else if (!add && --ctx->nr_cgroups)
863+
return;
864+
/*
865+
* Because cgroup events are always per-cpu events,
866+
* this will always be called from the right CPU.
867+
*/
868+
cpuctx = __get_cpu_context(ctx);
869+
cpuctx->cgrp = add ? event->cgrp : NULL;
870+
}
871+
846872
#else /* !CONFIG_CGROUP_PERF */
847873

848874
static inline bool
@@ -920,6 +946,13 @@ perf_cgroup_mark_enabled(struct perf_event *event,
920946
struct perf_event_context *ctx)
921947
{
922948
}
949+
950+
static inline void
951+
list_update_cgroup_event(struct perf_event *event,
952+
struct perf_event_context *ctx, bool add)
953+
{
954+
}
955+
923956
#endif
924957

925958
/*
@@ -1392,6 +1425,7 @@ ctx_group_list(struct perf_event *event, struct perf_event_context *ctx)
13921425
static void
13931426
list_add_event(struct perf_event *event, struct perf_event_context *ctx)
13941427
{
1428+
13951429
lockdep_assert_held(&ctx->lock);
13961430

13971431
WARN_ON_ONCE(event->attach_state & PERF_ATTACH_CONTEXT);
@@ -1412,8 +1446,7 @@ list_add_event(struct perf_event *event, struct perf_event_context *ctx)
14121446
list_add_tail(&event->group_entry, list);
14131447
}
14141448

1415-
if (is_cgroup_event(event))
1416-
ctx->nr_cgroups++;
1449+
list_update_cgroup_event(event, ctx, true);
14171450

14181451
list_add_rcu(&event->event_entry, &ctx->event_list);
14191452
ctx->nr_events++;
@@ -1581,8 +1614,6 @@ static void perf_group_attach(struct perf_event *event)
15811614
static void
15821615
list_del_event(struct perf_event *event, struct perf_event_context *ctx)
15831616
{
1584-
struct perf_cpu_context *cpuctx;
1585-
15861617
WARN_ON_ONCE(event->ctx != ctx);
15871618
lockdep_assert_held(&ctx->lock);
15881619

@@ -1594,20 +1625,7 @@ list_del_event(struct perf_event *event, struct perf_event_context *ctx)
15941625

15951626
event->attach_state &= ~PERF_ATTACH_CONTEXT;
15961627

1597-
if (is_cgroup_event(event)) {
1598-
ctx->nr_cgroups--;
1599-
/*
1600-
* Because cgroup events are always per-cpu events, this will
1601-
* always be called from the right CPU.
1602-
*/
1603-
cpuctx = __get_cpu_context(ctx);
1604-
/*
1605-
* If there are no more cgroup events then clear cgrp to avoid
1606-
* stale pointer in update_cgrp_time_from_cpuctx().
1607-
*/
1608-
if (!ctx->nr_cgroups)
1609-
cpuctx->cgrp = NULL;
1610-
}
1628+
list_update_cgroup_event(event, ctx, false);
16111629

16121630
ctx->nr_events--;
16131631
if (event->attr.inherit_stat)
@@ -1716,8 +1734,8 @@ static inline int pmu_filter_match(struct perf_event *event)
17161734
static inline int
17171735
event_filter_match(struct perf_event *event)
17181736
{
1719-
return (event->cpu == -1 || event->cpu == smp_processor_id())
1720-
&& perf_cgroup_match(event) && pmu_filter_match(event);
1737+
return (event->cpu == -1 || event->cpu == smp_processor_id()) &&
1738+
perf_cgroup_match(event) && pmu_filter_match(event);
17211739
}
17221740

17231741
static void
@@ -1737,8 +1755,8 @@ event_sched_out(struct perf_event *event,
17371755
* maintained, otherwise bogus information is return
17381756
* via read() for time_enabled, time_running:
17391757
*/
1740-
if (event->state == PERF_EVENT_STATE_INACTIVE
1741-
&& !event_filter_match(event)) {
1758+
if (event->state == PERF_EVENT_STATE_INACTIVE &&
1759+
!event_filter_match(event)) {
17421760
delta = tstamp - event->tstamp_stopped;
17431761
event->tstamp_running += delta;
17441762
event->tstamp_stopped = tstamp;
@@ -2236,10 +2254,15 @@ perf_install_in_context(struct perf_event_context *ctx,
22362254

22372255
lockdep_assert_held(&ctx->mutex);
22382256

2239-
event->ctx = ctx;
22402257
if (event->cpu != -1)
22412258
event->cpu = cpu;
22422259

2260+
/*
2261+
* Ensures that if we can observe event->ctx, both the event and ctx
2262+
* will be 'complete'. See perf_iterate_sb_cpu().
2263+
*/
2264+
smp_store_release(&event->ctx, ctx);
2265+
22432266
if (!task) {
22442267
cpu_function_call(cpu, __perf_install_in_context, event);
22452268
return;
@@ -5969,6 +5992,14 @@ static void perf_iterate_sb_cpu(perf_iterate_f output, void *data)
59695992
struct perf_event *event;
59705993

59715994
list_for_each_entry_rcu(event, &pel->list, sb_list) {
5995+
/*
5996+
* Skip events that are not fully formed yet; ensure that
5997+
* if we observe event->ctx, both event and ctx will be
5998+
* complete enough. See perf_install_in_context().
5999+
*/
6000+
if (!smp_load_acquire(&event->ctx))
6001+
continue;
6002+
59726003
if (event->state < PERF_EVENT_STATE_INACTIVE)
59736004
continue;
59746005
if (!event_filter_match(event))

‎tools/arch/x86/include/asm/cpufeatures.h

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -225,7 +225,6 @@
225225
#define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
226226
#define X86_FEATURE_ADX ( 9*32+19) /* The ADCX and ADOX instructions */
227227
#define X86_FEATURE_SMAP ( 9*32+20) /* Supervisor Mode Access Prevention */
228-
#define X86_FEATURE_PCOMMIT ( 9*32+22) /* PCOMMIT instruction */
229228
#define X86_FEATURE_CLFLUSHOPT ( 9*32+23) /* CLFLUSHOPT instruction */
230229
#define X86_FEATURE_CLWB ( 9*32+24) /* CLWB instruction */
231230
#define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */
@@ -301,16 +300,14 @@
301300
#define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
302301
#define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
303302
#define X86_BUG_SYSRET_SS_ATTRS X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
304-
#define X86_BUG_NULL_SEG X86_BUG(9) /* Nulling a selector preserves the base */
305-
#define X86_BUG_SWAPGS_FENCE X86_BUG(10) /* SWAPGS without input dep on GS */
306-
307-
308303
#ifdef CONFIG_X86_32
309304
/*
310305
* 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional
311306
* to avoid confusion.
312307
*/
313308
#define X86_BUG_ESPFIX X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */
314309
#endif
315-
310+
#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */
311+
#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */
312+
#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
316313
#endif /* _ASM_X86_CPUFEATURES_H */

‎tools/arch/x86/include/asm/disabled-features.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,5 +56,7 @@
5656
#define DISABLED_MASK14 0
5757
#define DISABLED_MASK15 0
5858
#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE)
59+
#define DISABLED_MASK17 0
60+
#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
5961

6062
#endif /* _ASM_X86_DISABLED_FEATURES_H */

‎tools/arch/x86/include/asm/required-features.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -99,5 +99,7 @@
9999
#define REQUIRED_MASK14 0
100100
#define REQUIRED_MASK15 0
101101
#define REQUIRED_MASK16 0
102+
#define REQUIRED_MASK17 0
103+
#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
102104

103105
#endif /* _ASM_X86_REQUIRED_FEATURES_H */

‎tools/arch/x86/include/uapi/asm/vmx.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,6 @@
7878
#define EXIT_REASON_PML_FULL 62
7979
#define EXIT_REASON_XSAVES 63
8080
#define EXIT_REASON_XRSTORS 64
81-
#define EXIT_REASON_PCOMMIT 65
8281

8382
#define VMX_EXIT_REASONS \
8483
{ EXIT_REASON_EXCEPTION_NMI, "EXCEPTION_NMI" }, \
@@ -127,8 +126,7 @@
127126
{ EXIT_REASON_INVVPID, "INVVPID" }, \
128127
{ EXIT_REASON_INVPCID, "INVPCID" }, \
129128
{ EXIT_REASON_XSAVES, "XSAVES" }, \
130-
{ EXIT_REASON_XRSTORS, "XRSTORS" }, \
131-
{ EXIT_REASON_PCOMMIT, "PCOMMIT" }
129+
{ EXIT_REASON_XRSTORS, "XRSTORS" }
132130

133131
#define VMX_ABORT_SAVE_GUEST_MSR_FAIL 1
134132
#define VMX_ABORT_LOAD_HOST_MSR_FAIL 4

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