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Merge tag 'pwm/for-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm
Pull pwm updates from Thierry Reding: "The changes for this cycle are across the board. The bulk of it is cleanups, but there's also new device support in some drivers as well as more conversions to the atomic API" * tag 'pwm/for-5.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: (24 commits) pwm: atmel: Remove useless symbolic definitions pwm: bcm-kona: Update macros to remove braces around numbers pwm: imx27: Only enable the clocks once in .get_state() pwm: rcar: Improve calculation of divider pwm: rcar: Remove legacy APIs pwm: rcar: Use "atomic" API on rcar_pwm_resume() pwm: rcar: Add support "atomic" API pwm: atmel: Add support for SAM9X60's PWM controller pwm: atmel: Add PWM binding for SAM9X60 pwm: atmel: Rename objects of type atmel_pwm_data pwm: atmel: Add support for controllers with 32 bit counters pwm: atmel: Add struct atmel_pwm_data pwm: Add MediaTek MT8183 display PWM driver support pwm: hibvt: Add hi3559v100 support dt-bindings: pwm: hibvt: Add hi3559v100 support pwm: hibvt: Use individual struct per of-data pwm: imx: Signedness bug in imx_pwm_get_state() pwm: imx: Split into two drivers pwm: imx: Don't print an error on -EPROBE_DEFER pwm: imx: Set driver data earlier simplifying the end of ->probe() ...
2 parents 3a186d3 + d7d9631 commit add8462

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lines changed

13 files changed

+474
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lines changed

‎Documentation/devicetree/bindings/pwm/atmel-pwm.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ Required properties:
55
- "atmel,at91sam9rl-pwm"
66
- "atmel,sama5d3-pwm"
77
- "atmel,sama5d2-pwm"
8+
- "microchip,sam9x60-pwm"
89
- reg: physical base address and length of the controller's registers
910
- #pwm-cells: Should be 3. See pwm.txt in this directory for a
1011
description of the cells format.

‎Documentation/devicetree/bindings/pwm/pwm-hibvt.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@ Required properties:
55
The SoC specific strings supported including:
66
"hisilicon,hi3516cv300-pwm"
77
"hisilicon,hi3519v100-pwm"
8+
"hisilicon,hi3559v100-shub-pwm"
9+
"hisilicon,hi3559v100-pwm
810
- reg: physical base address and length of the controller's registers.
911
- clocks: phandle and clock specifier of the PWM reference clock.
1012
- resets: phandle and reset specifier for the PWM controller reset.

‎drivers/pwm/Kconfig

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -192,14 +192,23 @@ config PWM_IMG
192192
To compile this driver as a module, choose M here: the module
193193
will be called pwm-img
194194

195-
config PWM_IMX
196-
tristate "i.MX PWM support"
195+
config PWM_IMX1
196+
tristate "i.MX1 PWM support"
197197
depends on ARCH_MXC
198198
help
199-
Generic PWM framework driver for i.MX.
199+
Generic PWM framework driver for i.MX1 and i.MX21
200200

201201
To compile this driver as a module, choose M here: the module
202-
will be called pwm-imx.
202+
will be called pwm-imx1.
203+
204+
config PWM_IMX27
205+
tristate "i.MX27 PWM support"
206+
depends on ARCH_MXC
207+
help
208+
Generic PWM framework driver for i.MX27 and later i.MX SoCs.
209+
210+
To compile this driver as a module, choose M here: the module
211+
will be called pwm-imx27.
203212

204213
config PWM_JZ4740
205214
tristate "Ingenic JZ47xx PWM support"

‎drivers/pwm/Makefile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,8 @@ obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o
1717
obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o
1818
obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o
1919
obj-$(CONFIG_PWM_IMG) += pwm-img.o
20-
obj-$(CONFIG_PWM_IMX) += pwm-imx.o
20+
obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o
21+
obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o
2122
obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o
2223
obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o
2324
obj-$(CONFIG_PWM_LPC18XX_SCT) += pwm-lpc18xx-sct.o

‎drivers/pwm/core.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -472,7 +472,10 @@ int pwm_apply_state(struct pwm_device *pwm, struct pwm_state *state)
472472
state->duty_cycle > state->period)
473473
return -EINVAL;
474474

475-
if (!memcmp(state, &pwm->state, sizeof(*state)))
475+
if (state->period == pwm->state.period &&
476+
state->duty_cycle == pwm->state.duty_cycle &&
477+
state->polarity == pwm->state.polarity &&
478+
state->enabled == pwm->state.enabled)
476479
return 0;
477480

478481
if (pwm->chip->ops->apply) {
@@ -1033,10 +1036,7 @@ static int pwm_seq_show(struct seq_file *s, void *v)
10331036
dev_name(chip->dev), chip->npwm,
10341037
(chip->npwm != 1) ? "s" : "");
10351038

1036-
if (chip->ops->dbg_show)
1037-
chip->ops->dbg_show(chip, s);
1038-
else
1039-
pwm_dbg_show(chip, s);
1039+
pwm_dbg_show(chip, s);
10401040

10411041
return 0;
10421042
}

‎drivers/pwm/pwm-atmel.c

Lines changed: 71 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -48,28 +48,28 @@
4848
#define PWMV2_CPRD 0x0C
4949
#define PWMV2_CPRDUPD 0x10
5050

51-
/*
52-
* Max value for duty and period
53-
*
54-
* Although the duty and period register is 32 bit,
55-
* however only the LSB 16 bits are significant.
56-
*/
57-
#define PWM_MAX_DTY 0xFFFF
58-
#define PWM_MAX_PRD 0xFFFF
59-
#define PRD_MAX_PRES 10
60-
6151
struct atmel_pwm_registers {
6252
u8 period;
6353
u8 period_upd;
6454
u8 duty;
6555
u8 duty_upd;
6656
};
6757

58+
struct atmel_pwm_config {
59+
u32 max_period;
60+
u32 max_pres;
61+
};
62+
63+
struct atmel_pwm_data {
64+
struct atmel_pwm_registers regs;
65+
struct atmel_pwm_config cfg;
66+
};
67+
6868
struct atmel_pwm_chip {
6969
struct pwm_chip chip;
7070
struct clk *clk;
7171
void __iomem *base;
72-
const struct atmel_pwm_registers *regs;
72+
const struct atmel_pwm_data *data;
7373

7474
unsigned int updated_pwms;
7575
/* ISR is cleared when read, ensure only one thread does that */
@@ -121,10 +121,10 @@ static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
121121
cycles *= clk_get_rate(atmel_pwm->clk);
122122
do_div(cycles, NSEC_PER_SEC);
123123

124-
for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1)
124+
for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1)
125125
(*pres)++;
126126

127-
if (*pres > PRD_MAX_PRES) {
127+
if (*pres > atmel_pwm->data->cfg.max_pres) {
128128
dev_err(chip->dev, "pres exceeds the maximum value\n");
129129
return -EINVAL;
130130
}
@@ -150,15 +150,15 @@ static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
150150
struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
151151
u32 val;
152152

153-
if (atmel_pwm->regs->duty_upd ==
154-
atmel_pwm->regs->period_upd) {
153+
if (atmel_pwm->data->regs.duty_upd ==
154+
atmel_pwm->data->regs.period_upd) {
155155
val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
156156
val &= ~PWM_CMR_UPD_CDTY;
157157
atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
158158
}
159159

160160
atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
161-
atmel_pwm->regs->duty_upd, cdty);
161+
atmel_pwm->data->regs.duty_upd, cdty);
162162
}
163163

164164
static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
@@ -168,9 +168,9 @@ static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
168168
struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
169169

170170
atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
171-
atmel_pwm->regs->duty, cdty);
171+
atmel_pwm->data->regs.duty, cdty);
172172
atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
173-
atmel_pwm->regs->period, cprd);
173+
atmel_pwm->data->regs.period, cprd);
174174
}
175175

176176
static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
@@ -225,7 +225,7 @@ static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
225225
cstate.polarity == state->polarity &&
226226
cstate.period == state->period) {
227227
cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
228-
atmel_pwm->regs->period);
228+
atmel_pwm->data->regs.period);
229229
atmel_pwm_calculate_cdty(state, cprd, &cdty);
230230
atmel_pwm_update_cdty(chip, pwm, cdty);
231231
return 0;
@@ -277,27 +277,55 @@ static const struct pwm_ops atmel_pwm_ops = {
277277
.owner = THIS_MODULE,
278278
};
279279

280-
static const struct atmel_pwm_registers atmel_pwm_regs_v1 = {
281-
.period = PWMV1_CPRD,
282-
.period_upd = PWMV1_CUPD,
283-
.duty = PWMV1_CDTY,
284-
.duty_upd = PWMV1_CUPD,
280+
static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
281+
.regs = {
282+
.period = PWMV1_CPRD,
283+
.period_upd = PWMV1_CUPD,
284+
.duty = PWMV1_CDTY,
285+
.duty_upd = PWMV1_CUPD,
286+
},
287+
.cfg = {
288+
/* 16 bits to keep period and duty. */
289+
.max_period = 0xffff,
290+
.max_pres = 10,
291+
},
292+
};
293+
294+
static const struct atmel_pwm_data atmel_sama5_pwm_data = {
295+
.regs = {
296+
.period = PWMV2_CPRD,
297+
.period_upd = PWMV2_CPRDUPD,
298+
.duty = PWMV2_CDTY,
299+
.duty_upd = PWMV2_CDTYUPD,
300+
},
301+
.cfg = {
302+
/* 16 bits to keep period and duty. */
303+
.max_period = 0xffff,
304+
.max_pres = 10,
305+
},
285306
};
286307

287-
static const struct atmel_pwm_registers atmel_pwm_regs_v2 = {
288-
.period = PWMV2_CPRD,
289-
.period_upd = PWMV2_CPRDUPD,
290-
.duty = PWMV2_CDTY,
291-
.duty_upd = PWMV2_CDTYUPD,
308+
static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
309+
.regs = {
310+
.period = PWMV1_CPRD,
311+
.period_upd = PWMV1_CUPD,
312+
.duty = PWMV1_CDTY,
313+
.duty_upd = PWMV1_CUPD,
314+
},
315+
.cfg = {
316+
/* 32 bits to keep period and duty. */
317+
.max_period = 0xffffffff,
318+
.max_pres = 10,
319+
},
292320
};
293321

294322
static const struct platform_device_id atmel_pwm_devtypes[] = {
295323
{
296324
.name = "at91sam9rl-pwm",
297-
.driver_data = (kernel_ulong_t)&atmel_pwm_regs_v1,
325+
.driver_data = (kernel_ulong_t)&atmel_sam9rl_pwm_data,
298326
}, {
299327
.name = "sama5d3-pwm",
300-
.driver_data = (kernel_ulong_t)&atmel_pwm_regs_v2,
328+
.driver_data = (kernel_ulong_t)&atmel_sama5_pwm_data,
301329
}, {
302330
/* sentinel */
303331
},
@@ -307,20 +335,23 @@ MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
307335
static const struct of_device_id atmel_pwm_dt_ids[] = {
308336
{
309337
.compatible = "atmel,at91sam9rl-pwm",
310-
.data = &atmel_pwm_regs_v1,
338+
.data = &atmel_sam9rl_pwm_data,
311339
}, {
312340
.compatible = "atmel,sama5d3-pwm",
313-
.data = &atmel_pwm_regs_v2,
341+
.data = &atmel_sama5_pwm_data,
314342
}, {
315343
.compatible = "atmel,sama5d2-pwm",
316-
.data = &atmel_pwm_regs_v2,
344+
.data = &atmel_sama5_pwm_data,
345+
}, {
346+
.compatible = "microchip,sam9x60-pwm",
347+
.data = &mchp_sam9x60_pwm_data,
317348
}, {
318349
/* sentinel */
319350
},
320351
};
321352
MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
322353

323-
static inline const struct atmel_pwm_registers *
354+
static inline const struct atmel_pwm_data *
324355
atmel_pwm_get_driver_data(struct platform_device *pdev)
325356
{
326357
const struct platform_device_id *id;
@@ -330,18 +361,18 @@ atmel_pwm_get_driver_data(struct platform_device *pdev)
330361

331362
id = platform_get_device_id(pdev);
332363

333-
return (struct atmel_pwm_registers *)id->driver_data;
364+
return (struct atmel_pwm_data *)id->driver_data;
334365
}
335366

336367
static int atmel_pwm_probe(struct platform_device *pdev)
337368
{
338-
const struct atmel_pwm_registers *regs;
369+
const struct atmel_pwm_data *data;
339370
struct atmel_pwm_chip *atmel_pwm;
340371
struct resource *res;
341372
int ret;
342373

343-
regs = atmel_pwm_get_driver_data(pdev);
344-
if (!regs)
374+
data = atmel_pwm_get_driver_data(pdev);
375+
if (!data)
345376
return -ENODEV;
346377

347378
atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
@@ -373,7 +404,7 @@ static int atmel_pwm_probe(struct platform_device *pdev)
373404

374405
atmel_pwm->chip.base = -1;
375406
atmel_pwm->chip.npwm = 4;
376-
atmel_pwm->regs = regs;
407+
atmel_pwm->data = data;
377408
atmel_pwm->updated_pwms = 0;
378409
mutex_init(&atmel_pwm->isr_lock);
379410

‎drivers/pwm/pwm-bcm-kona.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -45,25 +45,25 @@
4545
* high or low depending on its state at that exact instant.
4646
*/
4747

48-
#define PWM_CONTROL_OFFSET (0x00000000)
48+
#define PWM_CONTROL_OFFSET 0x00000000
4949
#define PWM_CONTROL_SMOOTH_SHIFT(chan) (24 + (chan))
5050
#define PWM_CONTROL_TYPE_SHIFT(chan) (16 + (chan))
5151
#define PWM_CONTROL_POLARITY_SHIFT(chan) (8 + (chan))
5252
#define PWM_CONTROL_TRIGGER_SHIFT(chan) (chan)
5353

54-
#define PRESCALE_OFFSET (0x00000004)
54+
#define PRESCALE_OFFSET 0x00000004
5555
#define PRESCALE_SHIFT(chan) ((chan) << 2)
5656
#define PRESCALE_MASK(chan) (0x7 << PRESCALE_SHIFT(chan))
57-
#define PRESCALE_MIN (0x00000000)
58-
#define PRESCALE_MAX (0x00000007)
57+
#define PRESCALE_MIN 0x00000000
58+
#define PRESCALE_MAX 0x00000007
5959

6060
#define PERIOD_COUNT_OFFSET(chan) (0x00000008 + ((chan) << 3))
61-
#define PERIOD_COUNT_MIN (0x00000002)
62-
#define PERIOD_COUNT_MAX (0x00ffffff)
61+
#define PERIOD_COUNT_MIN 0x00000002
62+
#define PERIOD_COUNT_MAX 0x00ffffff
6363

6464
#define DUTY_CYCLE_HIGH_OFFSET(chan) (0x0000000c + ((chan) << 3))
65-
#define DUTY_CYCLE_HIGH_MIN (0x00000000)
66-
#define DUTY_CYCLE_HIGH_MAX (0x00ffffff)
65+
#define DUTY_CYCLE_HIGH_MIN 0x00000000
66+
#define DUTY_CYCLE_HIGH_MAX 0x00ffffff
6767

6868
struct kona_pwmc {
6969
struct pwm_chip chip;

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