Skip to content

Commit aec8d5c

Browse files
Rex Zhualexdeucher
authored andcommitted
drm/amd/powerplay: delete dead code in smumgr
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 63196fe commit aec8d5c

File tree

2 files changed

+0
-119
lines changed

2 files changed

+0
-119
lines changed

drivers/gpu/drm/amd/powerplay/inc/smumgr.h

Lines changed: 0 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -101,30 +101,12 @@ extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
101101
extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
102102
uint16_t msg, uint32_t parameter);
103103

104-
extern int smum_wait_on_register(struct pp_hwmgr *hwmgr,
105-
uint32_t index, uint32_t value, uint32_t mask);
106-
107-
extern int smum_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
108-
uint32_t index, uint32_t value, uint32_t mask);
109-
110-
extern int smum_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
111-
uint32_t indirect_port, uint32_t index,
112-
uint32_t value, uint32_t mask);
113-
114-
115-
extern void smum_wait_for_indirect_register_unequal(
116-
struct pp_hwmgr *hwmgr,
117-
uint32_t indirect_port, uint32_t index,
118-
uint32_t value, uint32_t mask);
119-
120-
121104
extern int smu_allocate_memory(void *device, uint32_t size,
122105
enum cgs_gpu_mem_type type,
123106
uint32_t byte_align, uint64_t *mc_addr,
124107
void **kptr, void *handle);
125108

126109
extern int smu_free_memory(void *device, void *handle);
127-
extern int vega10_smum_init(struct pp_hwmgr *hwmgr);
128110

129111
extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
130112

@@ -147,19 +129,5 @@ extern int smum_populate_requested_graphic_levels(struct pp_hwmgr *hwmgr,
147129

148130
extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
149131

150-
#define SMUM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
151-
152-
#define SMUM_FIELD_MASK(reg, field) reg##__##field##_MASK
153-
154-
155-
#define SMUM_GET_FIELD(value, reg, field) \
156-
(((value) & SMUM_FIELD_MASK(reg, field)) \
157-
>> SMUM_FIELD_SHIFT(reg, field))
158-
159-
160-
#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \
161-
SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
162-
reg, field)
163-
164132

165133
#endif

drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c

Lines changed: 0 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -144,93 +144,6 @@ int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
144144
hwmgr, msg, parameter);
145145
}
146146

147-
/*
148-
* Returns once the part of the register indicated by the mask has
149-
* reached the given value.
150-
*/
151-
int smum_wait_on_register(struct pp_hwmgr *hwmgr,
152-
uint32_t index,
153-
uint32_t value, uint32_t mask)
154-
{
155-
uint32_t i;
156-
uint32_t cur_value;
157-
158-
if (hwmgr == NULL || hwmgr->device == NULL)
159-
return -EINVAL;
160-
161-
for (i = 0; i < hwmgr->usec_timeout; i++) {
162-
cur_value = cgs_read_register(hwmgr->device, index);
163-
if ((cur_value & mask) == (value & mask))
164-
break;
165-
udelay(1);
166-
}
167-
168-
/* timeout means wrong logic*/
169-
if (i == hwmgr->usec_timeout)
170-
return -1;
171-
172-
return 0;
173-
}
174-
175-
int smum_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
176-
uint32_t index,
177-
uint32_t value, uint32_t mask)
178-
{
179-
uint32_t i;
180-
uint32_t cur_value;
181-
182-
if (hwmgr == NULL)
183-
return -EINVAL;
184-
185-
for (i = 0; i < hwmgr->usec_timeout; i++) {
186-
cur_value = cgs_read_register(hwmgr->device,
187-
index);
188-
if ((cur_value & mask) != (value & mask))
189-
break;
190-
udelay(1);
191-
}
192-
193-
/* timeout means wrong logic */
194-
if (i == hwmgr->usec_timeout)
195-
return -1;
196-
197-
return 0;
198-
}
199-
200-
201-
/*
202-
* Returns once the part of the register indicated by the mask
203-
* has reached the given value.The indirect space is described by
204-
* giving the memory-mapped index of the indirect index register.
205-
*/
206-
int smum_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
207-
uint32_t indirect_port,
208-
uint32_t index,
209-
uint32_t value,
210-
uint32_t mask)
211-
{
212-
if (hwmgr == NULL || hwmgr->device == NULL)
213-
return -EINVAL;
214-
215-
cgs_write_register(hwmgr->device, indirect_port, index);
216-
return smum_wait_on_register(hwmgr, indirect_port + 1,
217-
mask, value);
218-
}
219-
220-
void smum_wait_for_indirect_register_unequal(
221-
struct pp_hwmgr *hwmgr,
222-
uint32_t indirect_port,
223-
uint32_t index,
224-
uint32_t value,
225-
uint32_t mask)
226-
{
227-
if (hwmgr == NULL || hwmgr->device == NULL)
228-
return;
229-
cgs_write_register(hwmgr->device, indirect_port, index);
230-
smum_wait_for_register_unequal(hwmgr, indirect_port + 1,
231-
value, mask);
232-
}
233-
234147
int smu_allocate_memory(void *device, uint32_t size,
235148
enum cgs_gpu_mem_type type,
236149
uint32_t byte_align, uint64_t *mc_addr,

0 commit comments

Comments
 (0)