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Lin MingIngo Molnar
Lin Ming
authored and
Ingo Molnar
committed
perf, x86: Add Intel SandyBridge CPU support
This patch adds basic SandyBridge support, including hardware cache events and PEBS events support. It has been tested on SandyBridge CPUs with perf stat and also with PEBS based profiling - both work fine. The patch does not affect other models. v2 -> v3: - fix PEBS event 0xd0 with right umask combinations - move snb pebs constraint assignment to intel_pmu_init v1 -> v2: - add more raw and PEBS events constraints - use offcore events for LLC-* cache events - remove the call to Nehalem workaround enable_all function Signed-off-by: Lin Ming <ming.m.lin@intel.com> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Stephane Eranian <eranian@google.com> Cc: Andi Kleen <andi@firstfloor.org> LKML-Reference: <1299072424.2175.24.camel@localhost> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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‎arch/x86/kernel/cpu/perf_event.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -166,8 +166,10 @@ struct cpu_hw_events {
166166
/*
167167
* Constraint on the Event code + UMask
168168
*/
169-
#define PEBS_EVENT_CONSTRAINT(c, n) \
169+
#define INTEL_UEVENT_CONSTRAINT(c, n) \
170170
EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
171+
#define PEBS_EVENT_CONSTRAINT(c, n) \
172+
INTEL_UEVENT_CONSTRAINT(c, n)
171173

172174
#define EVENT_CONSTRAINT_END \
173175
EVENT_CONSTRAINT(0, 0, 0)

‎arch/x86/kernel/cpu/perf_event_intel.c

Lines changed: 124 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,19 @@ static struct event_constraint intel_westmere_event_constraints[] =
7676
EVENT_CONSTRAINT_END
7777
};
7878

79+
static struct event_constraint intel_snb_event_constraints[] =
80+
{
81+
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
82+
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
83+
/* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
84+
INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
85+
INTEL_EVENT_CONSTRAINT(0xb7, 0x1), /* OFF_CORE_RESPONSE_0 */
86+
INTEL_EVENT_CONSTRAINT(0xbb, 0x8), /* OFF_CORE_RESPONSE_1 */
87+
INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
88+
INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
89+
EVENT_CONSTRAINT_END
90+
};
91+
7992
static struct event_constraint intel_gen_event_constraints[] =
8093
{
8194
FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
@@ -89,6 +102,106 @@ static u64 intel_pmu_event_map(int hw_event)
89102
return intel_perfmon_event_map[hw_event];
90103
}
91104

105+
static __initconst const u64 snb_hw_cache_event_ids
106+
[PERF_COUNT_HW_CACHE_MAX]
107+
[PERF_COUNT_HW_CACHE_OP_MAX]
108+
[PERF_COUNT_HW_CACHE_RESULT_MAX] =
109+
{
110+
[ C(L1D) ] = {
111+
[ C(OP_READ) ] = {
112+
[ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
113+
[ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
114+
},
115+
[ C(OP_WRITE) ] = {
116+
[ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
117+
[ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
118+
},
119+
[ C(OP_PREFETCH) ] = {
120+
[ C(RESULT_ACCESS) ] = 0x0,
121+
[ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
122+
},
123+
},
124+
[ C(L1I ) ] = {
125+
[ C(OP_READ) ] = {
126+
[ C(RESULT_ACCESS) ] = 0x0,
127+
[ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
128+
},
129+
[ C(OP_WRITE) ] = {
130+
[ C(RESULT_ACCESS) ] = -1,
131+
[ C(RESULT_MISS) ] = -1,
132+
},
133+
[ C(OP_PREFETCH) ] = {
134+
[ C(RESULT_ACCESS) ] = 0x0,
135+
[ C(RESULT_MISS) ] = 0x0,
136+
},
137+
},
138+
[ C(LL ) ] = {
139+
/*
140+
* TBD: Need Off-core Response Performance Monitoring support
141+
*/
142+
[ C(OP_READ) ] = {
143+
/* OFFCORE_RESPONSE_0.ANY_DATA.LOCAL_CACHE */
144+
[ C(RESULT_ACCESS) ] = 0x01b7,
145+
/* OFFCORE_RESPONSE_1.ANY_DATA.ANY_LLC_MISS */
146+
[ C(RESULT_MISS) ] = 0x01bb,
147+
},
148+
[ C(OP_WRITE) ] = {
149+
/* OFFCORE_RESPONSE_0.ANY_RFO.LOCAL_CACHE */
150+
[ C(RESULT_ACCESS) ] = 0x01b7,
151+
/* OFFCORE_RESPONSE_1.ANY_RFO.ANY_LLC_MISS */
152+
[ C(RESULT_MISS) ] = 0x01bb,
153+
},
154+
[ C(OP_PREFETCH) ] = {
155+
/* OFFCORE_RESPONSE_0.PREFETCH.LOCAL_CACHE */
156+
[ C(RESULT_ACCESS) ] = 0x01b7,
157+
/* OFFCORE_RESPONSE_1.PREFETCH.ANY_LLC_MISS */
158+
[ C(RESULT_MISS) ] = 0x01bb,
159+
},
160+
},
161+
[ C(DTLB) ] = {
162+
[ C(OP_READ) ] = {
163+
[ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
164+
[ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
165+
},
166+
[ C(OP_WRITE) ] = {
167+
[ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
168+
[ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
169+
},
170+
[ C(OP_PREFETCH) ] = {
171+
[ C(RESULT_ACCESS) ] = 0x0,
172+
[ C(RESULT_MISS) ] = 0x0,
173+
},
174+
},
175+
[ C(ITLB) ] = {
176+
[ C(OP_READ) ] = {
177+
[ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
178+
[ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
179+
},
180+
[ C(OP_WRITE) ] = {
181+
[ C(RESULT_ACCESS) ] = -1,
182+
[ C(RESULT_MISS) ] = -1,
183+
},
184+
[ C(OP_PREFETCH) ] = {
185+
[ C(RESULT_ACCESS) ] = -1,
186+
[ C(RESULT_MISS) ] = -1,
187+
},
188+
},
189+
[ C(BPU ) ] = {
190+
[ C(OP_READ) ] = {
191+
[ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
192+
[ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
193+
},
194+
[ C(OP_WRITE) ] = {
195+
[ C(RESULT_ACCESS) ] = -1,
196+
[ C(RESULT_MISS) ] = -1,
197+
},
198+
[ C(OP_PREFETCH) ] = {
199+
[ C(RESULT_ACCESS) ] = -1,
200+
[ C(RESULT_MISS) ] = -1,
201+
},
202+
},
203+
};
204+
92205
static __initconst const u64 westmere_hw_cache_event_ids
93206
[PERF_COUNT_HW_CACHE_MAX]
94207
[PERF_COUNT_HW_CACHE_OP_MAX]
@@ -1062,6 +1175,17 @@ static __init int intel_pmu_init(void)
10621175
pr_cont("Westmere events, ");
10631176
break;
10641177

1178+
case 42: /* SandyBridge */
1179+
memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
1180+
sizeof(hw_cache_event_ids));
1181+
1182+
intel_pmu_lbr_init_nhm();
1183+
1184+
x86_pmu.event_constraints = intel_snb_event_constraints;
1185+
x86_pmu.pebs_constraints = intel_snb_pebs_events;
1186+
pr_cont("SandyBridge events, ");
1187+
break;
1188+
10651189
default:
10661190
/*
10671191
* default constraints for v2 and up

‎arch/x86/kernel/cpu/perf_event_intel_ds.c

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -388,6 +388,44 @@ static struct event_constraint intel_nehalem_pebs_events[] = {
388388
EVENT_CONSTRAINT_END
389389
};
390390

391+
static struct event_constraint intel_snb_pebs_events[] = {
392+
PEBS_EVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
393+
PEBS_EVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
394+
PEBS_EVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
395+
PEBS_EVENT_CONSTRAINT(0x01c4, 0xf), /* BR_INST_RETIRED.CONDITIONAL */
396+
PEBS_EVENT_CONSTRAINT(0x02c4, 0xf), /* BR_INST_RETIRED.NEAR_CALL */
397+
PEBS_EVENT_CONSTRAINT(0x04c4, 0xf), /* BR_INST_RETIRED.ALL_BRANCHES */
398+
PEBS_EVENT_CONSTRAINT(0x08c4, 0xf), /* BR_INST_RETIRED.NEAR_RETURN */
399+
PEBS_EVENT_CONSTRAINT(0x10c4, 0xf), /* BR_INST_RETIRED.NOT_TAKEN */
400+
PEBS_EVENT_CONSTRAINT(0x20c4, 0xf), /* BR_INST_RETIRED.NEAR_TAKEN */
401+
PEBS_EVENT_CONSTRAINT(0x40c4, 0xf), /* BR_INST_RETIRED.FAR_BRANCH */
402+
PEBS_EVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
403+
PEBS_EVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
404+
PEBS_EVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
405+
PEBS_EVENT_CONSTRAINT(0x10c5, 0xf), /* BR_MISP_RETIRED.NOT_TAKEN */
406+
PEBS_EVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.TAKEN */
407+
PEBS_EVENT_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
408+
PEBS_EVENT_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORE */
409+
PEBS_EVENT_CONSTRAINT(0x11d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS_LOADS */
410+
PEBS_EVENT_CONSTRAINT(0x12d0, 0xf), /* MEM_UOP_RETIRED.STLB_MISS_STORES */
411+
PEBS_EVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOP_RETIRED.LOCK_LOADS */
412+
PEBS_EVENT_CONSTRAINT(0x22d0, 0xf), /* MEM_UOP_RETIRED.LOCK_STORES */
413+
PEBS_EVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOP_RETIRED.SPLIT_LOADS */
414+
PEBS_EVENT_CONSTRAINT(0x42d0, 0xf), /* MEM_UOP_RETIRED.SPLIT_STORES */
415+
PEBS_EVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOP_RETIRED.ANY_LOADS */
416+
PEBS_EVENT_CONSTRAINT(0x82d0, 0xf), /* MEM_UOP_RETIRED.ANY_STORES */
417+
PEBS_EVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
418+
PEBS_EVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
419+
PEBS_EVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.LLC_HIT */
420+
PEBS_EVENT_CONSTRAINT(0x40d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
421+
PEBS_EVENT_CONSTRAINT(0x01d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
422+
PEBS_EVENT_CONSTRAINT(0x02d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
423+
PEBS_EVENT_CONSTRAINT(0x04d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM */
424+
PEBS_EVENT_CONSTRAINT(0x08d2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE */
425+
PEBS_EVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
426+
EVENT_CONSTRAINT_END
427+
};
428+
391429
static struct event_constraint *
392430
intel_pebs_constraints(struct perf_event *event)
393431
{

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