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crypto: caam/qi - add ablkcipher and authenc algorithms
Add support to submit ablkcipher and authenc algorithms via the QI backend: -ablkcipher: cbc({aes,des,des3_ede}) ctr(aes), rfc3686(ctr(aes)) xts(aes) -authenc: authenc(hmac(md5),cbc({aes,des,des3_ede})) authenc(hmac(sha*),cbc({aes,des,des3_ede})) caam/qi being a new driver, let's wait some time to settle down without interfering with existing caam/jr driver. Accordingly, for now all caam/qi algorithms (caamalg_qi module) are marked to be of lower priority than caam/jr ones (caamalg module). Signed-off-by: Vakul Garg <vakul.garg@nxp.com> Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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‎drivers/crypto/caam/Kconfig

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,23 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
8787
To compile this as a module, choose M here: the module
8888
will be called caamalg.
8989

90+
config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI
91+
tristate "Queue Interface as Crypto API backend"
92+
depends on CRYPTO_DEV_FSL_CAAM_JR && FSL_DPAA && NET
93+
default y
94+
select CRYPTO_AUTHENC
95+
select CRYPTO_BLKCIPHER
96+
help
97+
Selecting this will use CAAM Queue Interface (QI) for sending
98+
& receiving crypto jobs to/from CAAM. This gives better performance
99+
than job ring interface when the number of cores are more than the
100+
number of job rings assigned to the kernel. The number of portals
101+
assigned to the kernel should also be more than the number of
102+
job rings.
103+
104+
To compile this as a module, choose M here: the module
105+
will be called caamalg_qi.
106+
90107
config CRYPTO_DEV_FSL_CAAM_AHASH_API
91108
tristate "Register hash algorithm implementations with Crypto API"
92109
depends on CRYPTO_DEV_FSL_CAAM_JR
@@ -136,4 +153,5 @@ config CRYPTO_DEV_FSL_CAAM_DEBUG
136153
information in the CAAM driver.
137154

138155
config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC
139-
def_tristate CRYPTO_DEV_FSL_CAAM_CRYPTO_API
156+
def_tristate (CRYPTO_DEV_FSL_CAAM_CRYPTO_API || \
157+
CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI)

‎drivers/crypto/caam/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ endif
88
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o
99
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o
1010
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
11+
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o
1112
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o
1213
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
1314
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o

‎drivers/crypto/caam/caamalg.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -266,8 +266,9 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
266266

267267
/* aead_encrypt shared descriptor */
268268
desc = ctx->sh_desc_enc;
269-
cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ctx->authsize,
270-
is_rfc3686, nonce, ctx1_iv_off);
269+
cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ivsize,
270+
ctx->authsize, is_rfc3686, nonce, ctx1_iv_off,
271+
false);
271272
dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
272273
desc_bytes(desc), DMA_TO_DEVICE);
273274

@@ -299,7 +300,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
299300
desc = ctx->sh_desc_dec;
300301
cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize,
301302
ctx->authsize, alg->caam.geniv, is_rfc3686,
302-
nonce, ctx1_iv_off);
303+
nonce, ctx1_iv_off, false);
303304
dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
304305
desc_bytes(desc), DMA_TO_DEVICE);
305306

@@ -333,7 +334,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
333334
desc = ctx->sh_desc_enc;
334335
cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize,
335336
ctx->authsize, is_rfc3686, nonce,
336-
ctx1_iv_off);
337+
ctx1_iv_off, false);
337338
dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
338339
desc_bytes(desc), DMA_TO_DEVICE);
339340

‎drivers/crypto/caam/caamalg_desc.c

Lines changed: 71 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -265,17 +265,19 @@ static void init_sh_desc_key_aead(u32 * const desc,
265265
* split key is to be used, the size of the split key itself is
266266
* specified. Valid algorithm values - one of OP_ALG_ALGSEL_{MD5, SHA1,
267267
* SHA224, SHA256, SHA384, SHA512} ANDed with OP_ALG_AAI_HMAC_PRECOMP.
268+
* @ivsize: initialization vector size
268269
* @icvsize: integrity check value (ICV) size (truncated or full)
269270
* @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
270271
* @nonce: pointer to rfc3686 nonce
271272
* @ctx1_iv_off: IV offset in CONTEXT1 register
273+
* @is_qi: true when called from caam/qi
272274
*
273275
* Note: Requires an MDHA split key.
274276
*/
275277
void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
276-
struct alginfo *adata, unsigned int icvsize,
277-
const bool is_rfc3686, u32 *nonce,
278-
const u32 ctx1_iv_off)
278+
struct alginfo *adata, unsigned int ivsize,
279+
unsigned int icvsize, const bool is_rfc3686,
280+
u32 *nonce, const u32 ctx1_iv_off, const bool is_qi)
279281
{
280282
/* Note: Context registers are saved. */
281283
init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
@@ -284,6 +286,25 @@ void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
284286
append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
285287
OP_ALG_ENCRYPT);
286288

289+
if (is_qi) {
290+
u32 *wait_load_cmd;
291+
292+
/* REG3 = assoclen */
293+
append_seq_load(desc, 4, LDST_CLASS_DECO |
294+
LDST_SRCDST_WORD_DECO_MATH3 |
295+
(4 << LDST_OFFSET_SHIFT));
296+
297+
wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
298+
JUMP_COND_CALM | JUMP_COND_NCP |
299+
JUMP_COND_NOP | JUMP_COND_NIP |
300+
JUMP_COND_NIFP);
301+
set_jump_tgt_here(desc, wait_load_cmd);
302+
303+
append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
304+
LDST_SRCDST_BYTE_CONTEXT |
305+
(ctx1_iv_off << LDST_OFFSET_SHIFT));
306+
}
307+
287308
/* Read and write assoclen bytes */
288309
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
289310
append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
@@ -338,14 +359,15 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_encap);
338359
* @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
339360
* @nonce: pointer to rfc3686 nonce
340361
* @ctx1_iv_off: IV offset in CONTEXT1 register
362+
* @is_qi: true when called from caam/qi
341363
*
342364
* Note: Requires an MDHA split key.
343365
*/
344366
void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
345367
struct alginfo *adata, unsigned int ivsize,
346368
unsigned int icvsize, const bool geniv,
347369
const bool is_rfc3686, u32 *nonce,
348-
const u32 ctx1_iv_off)
370+
const u32 ctx1_iv_off, const bool is_qi)
349371
{
350372
/* Note: Context registers are saved. */
351373
init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
@@ -354,6 +376,26 @@ void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
354376
append_operation(desc, adata->algtype | OP_ALG_AS_INITFINAL |
355377
OP_ALG_DECRYPT | OP_ALG_ICV_ON);
356378

379+
if (is_qi) {
380+
u32 *wait_load_cmd;
381+
382+
/* REG3 = assoclen */
383+
append_seq_load(desc, 4, LDST_CLASS_DECO |
384+
LDST_SRCDST_WORD_DECO_MATH3 |
385+
(4 << LDST_OFFSET_SHIFT));
386+
387+
wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
388+
JUMP_COND_CALM | JUMP_COND_NCP |
389+
JUMP_COND_NOP | JUMP_COND_NIP |
390+
JUMP_COND_NIFP);
391+
set_jump_tgt_here(desc, wait_load_cmd);
392+
393+
if (!geniv)
394+
append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
395+
LDST_SRCDST_BYTE_CONTEXT |
396+
(ctx1_iv_off << LDST_OFFSET_SHIFT));
397+
}
398+
357399
/* Read and write assoclen bytes */
358400
append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
359401
if (geniv)
@@ -423,21 +465,44 @@ EXPORT_SYMBOL(cnstr_shdsc_aead_decap);
423465
* @is_rfc3686: true when ctr(aes) is wrapped by rfc3686 template
424466
* @nonce: pointer to rfc3686 nonce
425467
* @ctx1_iv_off: IV offset in CONTEXT1 register
468+
* @is_qi: true when called from caam/qi
426469
*
427470
* Note: Requires an MDHA split key.
428471
*/
429472
void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
430473
struct alginfo *adata, unsigned int ivsize,
431474
unsigned int icvsize, const bool is_rfc3686,
432-
u32 *nonce, const u32 ctx1_iv_off)
475+
u32 *nonce, const u32 ctx1_iv_off,
476+
const bool is_qi)
433477
{
434478
u32 geniv, moveiv;
435479

436480
/* Note: Context registers are saved. */
437481
init_sh_desc_key_aead(desc, cdata, adata, is_rfc3686, nonce);
438482

439-
if (is_rfc3686)
483+
if (is_qi) {
484+
u32 *wait_load_cmd;
485+
486+
/* REG3 = assoclen */
487+
append_seq_load(desc, 4, LDST_CLASS_DECO |
488+
LDST_SRCDST_WORD_DECO_MATH3 |
489+
(4 << LDST_OFFSET_SHIFT));
490+
491+
wait_load_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
492+
JUMP_COND_CALM | JUMP_COND_NCP |
493+
JUMP_COND_NOP | JUMP_COND_NIP |
494+
JUMP_COND_NIFP);
495+
set_jump_tgt_here(desc, wait_load_cmd);
496+
}
497+
498+
if (is_rfc3686) {
499+
if (is_qi)
500+
append_seq_load(desc, ivsize, LDST_CLASS_1_CCB |
501+
LDST_SRCDST_BYTE_CONTEXT |
502+
(ctx1_iv_off << LDST_OFFSET_SHIFT));
503+
440504
goto copy_iv;
505+
}
441506

442507
/* Generate IV */
443508
geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |

‎drivers/crypto/caam/caamalg_desc.h

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,9 @@
1212
#define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 11 * CAAM_CMD_SZ)
1313
#define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 15 * CAAM_CMD_SZ)
1414
#define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
15+
#define DESC_QI_AEAD_ENC_LEN (DESC_AEAD_ENC_LEN + 3 * CAAM_CMD_SZ)
16+
#define DESC_QI_AEAD_DEC_LEN (DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ)
17+
#define DESC_QI_AEAD_GIVENC_LEN (DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ)
1518

1619
/* Note: Nonce is counted in cdata.keylen */
1720
#define DESC_AEAD_CTR_RFC3686_LEN (4 * CAAM_CMD_SZ)
@@ -45,20 +48,22 @@ void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata,
4548
unsigned int icvsize);
4649

4750
void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
48-
struct alginfo *adata, unsigned int icvsize,
49-
const bool is_rfc3686, u32 *nonce,
50-
const u32 ctx1_iv_off);
51+
struct alginfo *adata, unsigned int ivsize,
52+
unsigned int icvsize, const bool is_rfc3686,
53+
u32 *nonce, const u32 ctx1_iv_off,
54+
const bool is_qi);
5155

5256
void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
5357
struct alginfo *adata, unsigned int ivsize,
5458
unsigned int icvsize, const bool geniv,
5559
const bool is_rfc3686, u32 *nonce,
56-
const u32 ctx1_iv_off);
60+
const u32 ctx1_iv_off, const bool is_qi);
5761

5862
void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
5963
struct alginfo *adata, unsigned int ivsize,
6064
unsigned int icvsize, const bool is_rfc3686,
61-
u32 *nonce, const u32 ctx1_iv_off);
65+
u32 *nonce, const u32 ctx1_iv_off,
66+
const bool is_qi);
6267

6368
void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata,
6469
unsigned int icvsize);

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