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Merge tag 'drm-intel-next-2018-09-06-2' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
Merge tag 'gvt-next-2018-09-04' drm-intel-next-2018-09-06-1: UAPI Changes: - GGTT coherency GETPARAM: GGTT has turned out to be non-coherent for some platforms, which we've failed to communicate to userspace so far. SNA was modified to do extra flushing on non-coherent GGTT access, while Mesa will mitigate by always requiring WC mapping (which is non-coherent anyway). - Neuter Resource Streamer uAPI: There never really were users for the feature, so neuter it while keeping the interface bits for compatibility. This is a long due item from past. Cross-subsystem Changes: - Backmerge of branch drm-next-4.19 for DP_DPCD_REV_14 changes Core Changes: - None Driver Changes: - A load of Icelake (ICL) enabling patches (Paulo, Manasi) - Enabled full PPGTT for IVB,VLV and HSW (Chris) - Bugzilla #107113: Distribute DDB based on display resolutions (Mahesh) - Bugzillas #100023,#107476,#94921: Support limited range DP displays (Jani) - Bugzilla #107503: Increase LSPCON timeout (Fredrik) - Avoid boosting GPU due to an occasional stall in interactive workloads (Chris) - Apply GGTT coherency W/A only for affected systems instead of all (Chris) - Fix for infinite link training loop for faulty USB-C MST hubs (Nathan) - Keep KMS functional on Gen4 and earlier when GPU is wedged (Chris) - Stop holding ppGTT reference from closed VMAs (Chris) - Clear error registers after error capture (Lionel) - Various Icelake fixes (Anusha, Jyoti, Ville, Tvrtko) - Add missing Coffeelake (CFL) PCI IDs (Rodrigo) - Flush execlists tasklet directly from reset-finish (Chris) - Fix LPE audio runtime PM (Chris) - Fix detection of out of range surface positions (GLK/CNL) (Ville) - Remove wait-for-idle for PSR2 (Dhinakaran) - Power down existing display hardware resources when display is disabled (Chris) - Don't allow runtime power management if RC6 doesn't exist (Chris) - Add debugging checks for runtime power management paths (Imre) - Increase symmetry in display power init/fini paths (Imre) - Isolate GVT specific macros from i915_reg.h (Lucas) - Increase symmetry in power management enable/disable paths (Chris) - Increase IP disable timeout to 100 ms to avoid DRM_ERROR (Imre) - Fix memory leak from HDMI HDCP write function (Brian, Rodrigo) - Reject Y/Yf tiling on interlaced modes (Ville) - Use a cached mapping for the physical HWS on older gens (Chris) - Force slow path of writing relocations to buffer if unable to write to userspace (Chris) - Do a full device reset after being wedged (Chris) - Keep forcewake counts over reset (in case of debugfs user) (Imre, Chris) - Avoid false-positive errors from power wells during init (Imre) - Reset engines forcibly in exchange of declaring whole device wedged (Mika) - Reduce context HW ID lifetime in preparation for Icelake (Chris) - Attempt to recover from module load failures (Chris) - Keep select interrupts over a reset to avoid missing/losing them (Chris) - GuC submission backend improvements (Jakub) - Terminate context images with BB_END (Chris, Lionel) - Make GCC evaluate GGTT view struct size assertions again (Ville) - Add selftest to exercise suspend/hibernate code-paths for GEM (Chris) - Use a full emulation of a user ppgtt context in selftests (Chris) - Exercise resetting in the middle of a wait-on-fence in selftests (Chris) - Fix coherency issues on selftests for Baytrail (Chris) - Various other GEM fixes / self-test updates (Chris, Matt) - GuC doorbell self-tests (Daniele) - PSR mode control through debugfs for IGTs (Maarten) - Degrade expected WM latency errors to DRM_DEBUG_KMS (Chris) - Cope with errors better in MST link training (Dhinakaran) - Fix WARN on KBL external displays (Azhar) - Power well code cleanups (Imre) - Fixes to PSR debugging (Dhinakaran) - Make forcewake errors louder for easier catching in CI (WARNs) (Chris) - Fortify tiling code against programmer errors (Chris) - Bunch of fixes for CI exposed corner cases (multiple authors, mostly Chris) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180907105446.GA22860@jlahtine-desk.ger.corp.intel.com
2 parents 1f3eb34 + a28957b commit b1c1566

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lines changed

‎drivers/gpu/drm/i915/Kconfig.debug

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ config DRM_I915_DEBUG
3030
select SW_SYNC # signaling validation framework (igt/syncobj*)
3131
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
3232
select DRM_I915_SELFTEST
33+
select DRM_I915_DEBUG_RUNTIME_PM
3334
default n
3435
help
3536
Choose this option to turn on extra driver debugging that may affect
@@ -167,3 +168,14 @@ config DRM_I915_DEBUG_VBLANK_EVADE
167168
the vblank.
168169

169170
If in doubt, say "N".
171+
172+
config DRM_I915_DEBUG_RUNTIME_PM
173+
bool "Enable extra state checking for runtime PM"
174+
depends on DRM_I915
175+
default n
176+
help
177+
Choose this option to turn on extra state checking for the
178+
runtime PM functionality. This may introduce overhead during
179+
driver loading, suspend and resume operations.
180+
181+
If in doubt, say "N"

‎drivers/gpu/drm/i915/gvt/cfg_space.c

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,10 @@ static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = {
5656

5757
/**
5858
* vgpu_pci_cfg_mem_write - write virtual cfg space memory
59+
* @vgpu: target vgpu
60+
* @off: offset
61+
* @src: src ptr to write
62+
* @bytes: number of bytes
5963
*
6064
* Use this function to write virtual cfg space memory.
6165
* For standard cfg space, only RW bits can be changed,
@@ -91,6 +95,10 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off,
9195

9296
/**
9397
* intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
98+
* @vgpu: target vgpu
99+
* @offset: offset
100+
* @p_data: return data ptr
101+
* @bytes: number of bytes to read
94102
*
95103
* Returns:
96104
* Zero on success, negative error code if failed.
@@ -278,6 +286,10 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
278286

279287
/**
280288
* intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
289+
* @vgpu: target vgpu
290+
* @offset: offset
291+
* @p_data: write data ptr
292+
* @bytes: number of bytes to write
281293
*
282294
* Returns:
283295
* Zero on success, negative error code if failed.

‎drivers/gpu/drm/i915/gvt/cmd_parser.c

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1840,6 +1840,8 @@ static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
18401840
return ret;
18411841
}
18421842

1843+
static int mi_noop_index;
1844+
18431845
static struct cmd_info cmd_info[] = {
18441846
{"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
18451847

@@ -2525,7 +2527,12 @@ static int cmd_parser_exec(struct parser_exec_state *s)
25252527

25262528
cmd = cmd_val(s, 0);
25272529

2528-
info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2530+
/* fastpath for MI_NOOP */
2531+
if (cmd == MI_NOOP)
2532+
info = &cmd_info[mi_noop_index];
2533+
else
2534+
info = get_cmd_info(s->vgpu->gvt, cmd, s->ring_id);
2535+
25292536
if (info == NULL) {
25302537
gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %d, workload=%p\n",
25312538
cmd, get_opcode(cmd, s->ring_id),
@@ -2928,6 +2935,8 @@ static int init_cmd_table(struct intel_gvt *gvt)
29282935
kfree(e);
29292936
return -EEXIST;
29302937
}
2938+
if (cmd_info[i].opcode == OP_MI_NOOP)
2939+
mi_noop_index = i;
29312940

29322941
INIT_HLIST_NODE(&e->hlist);
29332942
add_cmd_entry(gvt, e);

‎drivers/gpu/drm/i915/gvt/display.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -462,6 +462,7 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
462462
/**
463463
* intel_vgpu_init_display- initialize vGPU virtual display emulation
464464
* @vgpu: a vGPU
465+
* @resolution: resolution index for intel_vgpu_edid
465466
*
466467
* This function is used to initialize vGPU virtual display emulation stuffs
467468
*

‎drivers/gpu/drm/i915/gvt/edid.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -340,6 +340,9 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
340340
/**
341341
* intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
342342
* @vgpu: a vGPU
343+
* @offset: reg offset
344+
* @p_data: data return buffer
345+
* @bytes: access data length
343346
*
344347
* This function is used to emulate gmbus register mmio read
345348
*
@@ -365,6 +368,9 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
365368
/**
366369
* intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
367370
* @vgpu: a vGPU
371+
* @offset: reg offset
372+
* @p_data: data return buffer
373+
* @bytes: access data length
368374
*
369375
* This function is used to emulate gmbus register mmio write
370376
*
@@ -437,6 +443,9 @@ static inline int get_aux_ch_reg(unsigned int offset)
437443
/**
438444
* intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
439445
* @vgpu: a vGPU
446+
* @port_idx: port index
447+
* @offset: reg offset
448+
* @p_data: write ptr
440449
*
441450
* This function is used to emulate AUX channel register write
442451
*

‎drivers/gpu/drm/i915/gvt/gtt.c

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1113,6 +1113,10 @@ static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
11131113
}
11141114

11151115
/**
1116+
* Check if can do 2M page
1117+
* @vgpu: target vgpu
1118+
* @entry: target pfn's gtt entry
1119+
*
11161120
* Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
11171121
* negtive if found err.
11181122
*/
@@ -1945,7 +1949,7 @@ void intel_vgpu_unpin_mm(struct intel_vgpu_mm *mm)
19451949

19461950
/**
19471951
* intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
1948-
* @vgpu: a vGPU
1952+
* @mm: target vgpu mm
19491953
*
19501954
* This function is called when user wants to use a vGPU mm object. If this
19511955
* mm object hasn't been shadowed yet, the shadow will be populated at this
@@ -2521,8 +2525,7 @@ static int setup_spt_oos(struct intel_gvt *gvt)
25212525
/**
25222526
* intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
25232527
* @vgpu: a vGPU
2524-
* @page_table_level: PPGTT page table level
2525-
* @root_entry: PPGTT page table root pointers
2528+
* @pdps: pdp root array
25262529
*
25272530
* This function is used to find a PPGTT mm object from mm object pool
25282531
*

‎drivers/gpu/drm/i915/gvt/gvt.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -189,7 +189,6 @@ static const struct intel_gvt_ops intel_gvt_ops = {
189189

190190
/**
191191
* intel_gvt_init_host - Load MPT modules and detect if we're running in host
192-
* @gvt: intel gvt device
193192
*
194193
* This function is called at the driver loading stage. If failed to find a
195194
* loadable MPT module or detect currently we're running in a VM, then GVT-g
@@ -303,7 +302,7 @@ static int init_service_thread(struct intel_gvt *gvt)
303302

304303
/**
305304
* intel_gvt_clean_device - clean a GVT device
306-
* @gvt: intel gvt device
305+
* @dev_priv: i915 private
307306
*
308307
* This function is called at the driver unloading stage, to free the
309308
* resources owned by a GVT device.

‎drivers/gpu/drm/i915/gvt/handlers.c

Lines changed: 12 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1287,12 +1287,13 @@ static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
12871287
{
12881288
write_vreg(vgpu, offset, p_data, bytes);
12891289

1290-
if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_CTL_REQ(HSW_DISP_PW_GLOBAL))
1290+
if (vgpu_vreg(vgpu, offset) &
1291+
HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
12911292
vgpu_vreg(vgpu, offset) |=
1292-
HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
1293+
HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
12931294
else
12941295
vgpu_vreg(vgpu, offset) &=
1295-
~HSW_PWR_WELL_CTL_STATE(HSW_DISP_PW_GLOBAL);
1296+
~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
12961297
return 0;
12971298
}
12981299

@@ -2118,7 +2119,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
21182119

21192120
MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
21202121
gmbus_mmio_write);
2121-
MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2122+
MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
21222123
MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
21232124

21242125
MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
@@ -2443,17 +2444,10 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
24432444
MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
24442445
MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
24452446
MMIO_D(GEN6_PMINTRMSK, D_ALL);
2446-
/*
2447-
* Use an arbitrary power well controlled by the PWR_WELL_CTL
2448-
* register.
2449-
*/
2450-
MMIO_DH(HSW_PWR_WELL_CTL_BIOS(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2451-
power_well_ctl_mmio_write);
2452-
MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2453-
power_well_ctl_mmio_write);
2454-
MMIO_DH(HSW_PWR_WELL_CTL_KVMR, D_BDW, NULL, power_well_ctl_mmio_write);
2455-
MMIO_DH(HSW_PWR_WELL_CTL_DEBUG(HSW_DISP_PW_GLOBAL), D_BDW, NULL,
2456-
power_well_ctl_mmio_write);
2447+
MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2448+
MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2449+
MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2450+
MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
24572451
MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
24582452
MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
24592453

@@ -2804,13 +2798,8 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
28042798
MMIO_F(_MMIO(_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
28052799
dp_aux_ch_ctl_mmio_write);
28062800

2807-
/*
2808-
* Use an arbitrary power well controlled by the PWR_WELL_CTL
2809-
* register.
2810-
*/
2811-
MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);
2812-
MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,
2813-
skl_power_well_ctl_write);
2801+
MMIO_D(HSW_PWR_WELL_CTL1, D_SKL_PLUS);
2802+
MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
28142803

28152804
MMIO_D(_MMIO(0xa210), D_SKL_PLUS);
28162805
MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
@@ -3434,6 +3423,7 @@ bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
34343423
* @offset: register offset
34353424
* @pdata: data buffer
34363425
* @bytes: data length
3426+
* @is_read: read or write
34373427
*
34383428
* Returns:
34393429
* Zero on success, negative error code if failed.

‎drivers/gpu/drm/i915/gvt/kvmgt.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1712,7 +1712,7 @@ static unsigned long kvmgt_gfn_to_pfn(unsigned long handle, unsigned long gfn)
17121712
return pfn;
17131713
}
17141714

1715-
int kvmgt_dma_map_guest_page(unsigned long handle, unsigned long gfn,
1715+
static int kvmgt_dma_map_guest_page(unsigned long handle, unsigned long gfn,
17161716
unsigned long size, dma_addr_t *dma_addr)
17171717
{
17181718
struct kvmgt_guest_info *info;
@@ -1761,7 +1761,7 @@ static void __gvt_dma_release(struct kref *ref)
17611761
__gvt_cache_remove_entry(entry->vgpu, entry);
17621762
}
17631763

1764-
void kvmgt_dma_unmap_guest_page(unsigned long handle, dma_addr_t dma_addr)
1764+
static void kvmgt_dma_unmap_guest_page(unsigned long handle, dma_addr_t dma_addr)
17651765
{
17661766
struct kvmgt_guest_info *info;
17671767
struct gvt_dma *entry;

‎drivers/gpu/drm/i915/gvt/mmio.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@
3939
/**
4040
* intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
4141
* @vgpu: a vGPU
42+
* @gpa: guest physical address
4243
*
4344
* Returns:
4445
* Zero on success, negative error code if failed
@@ -228,7 +229,7 @@ int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
228229
/**
229230
* intel_vgpu_reset_mmio - reset virtual MMIO space
230231
* @vgpu: a vGPU
231-
*
232+
* @dmlr: whether this is device model level reset
232233
*/
233234
void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
234235
{

‎drivers/gpu/drm/i915/gvt/mmio_context.c

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -37,19 +37,6 @@
3737
#include "gvt.h"
3838
#include "trace.h"
3939

40-
/**
41-
* Defined in Intel Open Source PRM.
42-
* Ref: https://01.org/linuxgraphics/documentation/hardware-specification-prms
43-
*/
44-
#define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i)*4)
45-
#define TRNULLDETCT _MMIO(0x4de8)
46-
#define TRINVTILEDETCT _MMIO(0x4dec)
47-
#define TRVADR _MMIO(0x4df0)
48-
#define TRTTE _MMIO(0x4df4)
49-
#define RING_EXCC(base) _MMIO((base) + 0x28)
50-
#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
51-
#define VF_GUARDBAND _MMIO(0x83a4)
52-
5340
#define GEN9_MOCS_SIZE 64
5441

5542
/* Raw offset is appened to each line for convenience. */

‎drivers/gpu/drm/i915/gvt/mmio_context.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -53,5 +53,8 @@ bool is_inhibit_context(struct intel_context *ce);
5353

5454
int intel_vgpu_restore_inhibit_context(struct intel_vgpu *vgpu,
5555
struct i915_request *req);
56+
#define IS_RESTORE_INHIBIT(a) \
57+
(_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) == \
58+
((a) & _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT)))
5659

5760
#endif

‎drivers/gpu/drm/i915/gvt/opregion.c

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,6 @@ static void virt_vbt_generation(struct vbt *v)
216216
/**
217217
* intel_vgpu_init_opregion - initialize the stuff used to emulate opregion
218218
* @vgpu: a vGPU
219-
* @gpa: guest physical address of opregion
220219
*
221220
* Returns:
222221
* Zero on success, negative error code if failed.

‎drivers/gpu/drm/i915/gvt/page_track.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,8 @@ struct intel_vgpu_page_track *intel_vgpu_find_page_track(
4141
* intel_vgpu_register_page_track - register a guest page to be tacked
4242
* @vgpu: a vGPU
4343
* @gfn: the gfn of guest page
44+
* @handler: page track handler
45+
* @priv: tracker private
4446
*
4547
* Returns:
4648
* zero on success, negative error code if failed.

‎drivers/gpu/drm/i915/gvt/reg.h

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,4 +77,22 @@
7777
#define _RING_CTL_BUF_SIZE(ctl) (((ctl) & RB_TAIL_SIZE_MASK) + \
7878
I915_GTT_PAGE_SIZE)
7979

80+
#define PCH_GPIO_BASE _MMIO(0xc5010)
81+
82+
#define PCH_GMBUS0 _MMIO(0xc5100)
83+
#define PCH_GMBUS1 _MMIO(0xc5104)
84+
#define PCH_GMBUS2 _MMIO(0xc5108)
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#define PCH_GMBUS3 _MMIO(0xc510c)
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#define PCH_GMBUS4 _MMIO(0xc5110)
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#define PCH_GMBUS5 _MMIO(0xc5120)
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#define TRVATTL3PTRDW(i) _MMIO(0x4de0 + (i) * 4)
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#define TRNULLDETCT _MMIO(0x4de8)
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#define TRINVTILEDETCT _MMIO(0x4dec)
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#define TRVADR _MMIO(0x4df0)
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#define TRTTE _MMIO(0x4df4)
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#define RING_EXCC(base) _MMIO((base) + 0x28)
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#define RING_GFX_MODE(base) _MMIO((base) + 0x29c)
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#define VF_GUARDBAND _MMIO(0x83a4)
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#endif

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