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Merge tag 'edac_for_4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
Pull EDAC updates from Borislav Petkov: - Support for ZynqMP DDR controller support to synopsys_edac along with a driver cleanup and generalization for the addition of support for the new IP. (Manish Narani) - Removal of the /sys/bus/edac devices hierarchy. This enabled us to get rid of the silly memory controllers maximum number notion. (Tony Luck and Borislav Petkov) - skx_edac improvements and fixes. (Qiuxu Zhuo and Tony Luck) - The usual garden variety of small cleanups and fixes. * tag 'edac_for_4.21' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: (25 commits) EDAC, fsl_ddr: Add LS1021A to the list of supported hardware EDAC, i5000: Remove set but not used local variables MAINTAINERS, EDAC: Drop bouncing email EDAC, i82975x: Fix spelling mistake "reserverd" -> "reserved" EDAC, fsl: Move error injection under CONFIG_EDAC_DEBUG EDAC, skx: Let EDAC core show the decoded result for debugfs EDAC, skx: Move debugfs node under EDAC's hierarchy EDAC, skx: Prepend hex formatting with '0x' EDAC, skx: Fix function calling order in skx_exit() EDAC: Drop per-memory controller buses EDAC: Don't add devices under /sys/bus/edac EDAC: Fix indentation issues in several EDAC drivers EDAC, skx: Fix randconfig builds in a better way EDAC, i82975x: Remove set but not used variable dtype EDAC, qcom_edac: Remove irq_handled local variable EDAC, synopsys: Add Error Injection support for ZynqMP DDR controller EDAC, synopsys: Add ECC support for ZynqMP DDR controller EDAC, synopsys: Add macro defines for ZynqMP DDRC dt: bindings: Document ZynqMP DDRC in Synopsys documentation EDAC, synopsys: Add error handling for the of_device_get_match_data() result ...
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‎Documentation/devicetree/bindings/memory-controllers/synopsys.txt

Lines changed: 22 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,32 @@
11
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
22

3-
This controller has an optional ECC support in half-bus width (16-bit)
4-
configuration. The ECC controller corrects one bit error and detects
5-
two bit errors.
3+
The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
4+
bus width configurations.
5+
6+
The Zynq DDR ECC controller has an optional ECC support in half-bus width
7+
(16-bit) configuration.
8+
9+
These both ECC controllers correct single bit ECC errors and detect double bit
10+
ECC errors.
611

712
Required properties:
8-
- compatible: Should be 'xlnx,zynq-ddrc-a05'
9-
- reg: Base address and size of the controllers memory area
13+
- compatible: One of:
14+
- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15+
- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
16+
- reg: Should contain DDR controller registers location and length.
17+
18+
Required properties for "xlnx,zynqmp-ddrc-2.40a":
19+
- interrupts: Property with a value describing the interrupt number.
1020

1121
Example:
1222
memory-controller@f8006000 {
1323
compatible = "xlnx,zynq-ddrc-a05";
1424
reg = <0xf8006000 0x1000>;
1525
};
26+
27+
mc: memory-controller@fd070000 {
28+
compatible = "xlnx,zynqmp-ddrc-2.40a";
29+
reg = <0x0 0xfd070000 0x0 0x30000>;
30+
interrupt-parent = <&gic>;
31+
interrupts = <0 112 4>;
32+
};

‎MAINTAINERS

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5445,7 +5445,6 @@ S: Maintained
54455445
F: drivers/edac/i82443bxgx_edac.c
54465446

54475447
EDAC-I82975X
5448-
M: Ranganathan Desikan <ravi@jetztechnologies.com>
54495448
M: "Arvind R." <arvino55@gmail.com>
54505449
L: linux-edac@vger.kernel.org
54515450
S: Maintained

‎drivers/edac/Kconfig

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -231,10 +231,10 @@ config EDAC_SBRIDGE
231231

232232
config EDAC_SKX
233233
tristate "Intel Skylake server Integrated MC"
234-
depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
234+
depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
235235
depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
236236
select DMI
237-
select ACPI_ADXL if ACPI
237+
select ACPI_ADXL
238238
help
239239
Support for error detection and correction the Intel
240240
Skylake server Integrated Memory Controllers. If your
@@ -442,7 +442,7 @@ config EDAC_ALTERA_SDMMC
442442

443443
config EDAC_SYNOPSYS
444444
tristate "Synopsys DDR Memory Controller"
445-
depends on ARCH_ZYNQ
445+
depends on ARCH_ZYNQ || ARCH_ZYNQMP
446446
help
447447
Support for error detection and correction on the Synopsys DDR
448448
memory controller.

‎drivers/edac/e752x_edac.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1446,8 +1446,8 @@ static int __init e752x_init(void)
14461446

14471447
edac_dbg(3, "\n");
14481448

1449-
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
1450-
opstate_init();
1449+
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
1450+
opstate_init();
14511451

14521452
pci_rc = pci_register_driver(&e752x_driver);
14531453
return (pci_rc < 0) ? pci_rc : 0;

‎drivers/edac/edac_mc.c

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -55,8 +55,6 @@ static LIST_HEAD(mc_devices);
5555
*/
5656
static const char *edac_mc_owner;
5757

58-
static struct bus_type mc_bus[EDAC_MAX_MCS];
59-
6058
int edac_get_report_status(void)
6159
{
6260
return edac_report;
@@ -716,11 +714,6 @@ int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
716714
int ret = -EINVAL;
717715
edac_dbg(0, "\n");
718716

719-
if (mci->mc_idx >= EDAC_MAX_MCS) {
720-
pr_warn_once("Too many memory controllers: %d\n", mci->mc_idx);
721-
return -ENODEV;
722-
}
723-
724717
#ifdef CONFIG_EDAC_DEBUG
725718
if (edac_debug_level >= 3)
726719
edac_mc_dump_mci(mci);
@@ -760,7 +753,7 @@ int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci,
760753
/* set load time so that error rate can be tracked */
761754
mci->start_time = jiffies;
762755

763-
mci->bus = &mc_bus[mci->mc_idx];
756+
mci->bus = edac_get_sysfs_subsys();
764757

765758
if (edac_create_sysfs_mci_device(mci, groups)) {
766759
edac_mc_printk(mci, KERN_WARNING,

‎drivers/edac/edac_mc_sysfs.c

Lines changed: 2 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -405,7 +405,6 @@ static int edac_create_csrow_object(struct mem_ctl_info *mci,
405405
struct csrow_info *csrow, int index)
406406
{
407407
csrow->dev.type = &csrow_attr_type;
408-
csrow->dev.bus = mci->bus;
409408
csrow->dev.groups = csrow_dev_groups;
410409
device_initialize(&csrow->dev);
411410
csrow->dev.parent = &mci->dev;
@@ -636,7 +635,6 @@ static int edac_create_dimm_object(struct mem_ctl_info *mci,
636635
dimm->mci = mci;
637636

638637
dimm->dev.type = &dimm_attr_type;
639-
dimm->dev.bus = mci->bus;
640638
device_initialize(&dimm->dev);
641639

642640
dimm->dev.parent = &mci->dev;
@@ -914,33 +912,13 @@ static const struct device_type mci_attr_type = {
914912
int edac_create_sysfs_mci_device(struct mem_ctl_info *mci,
915913
const struct attribute_group **groups)
916914
{
917-
char *name;
918915
int i, err;
919916

920-
/*
921-
* The memory controller needs its own bus, in order to avoid
922-
* namespace conflicts at /sys/bus/edac.
923-
*/
924-
name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
925-
if (!name)
926-
return -ENOMEM;
927-
928-
mci->bus->name = name;
929-
930-
edac_dbg(0, "creating bus %s\n", mci->bus->name);
931-
932-
err = bus_register(mci->bus);
933-
if (err < 0) {
934-
kfree(name);
935-
return err;
936-
}
937-
938917
/* get the /sys/devices/system/edac subsys reference */
939918
mci->dev.type = &mci_attr_type;
940919
device_initialize(&mci->dev);
941920

942921
mci->dev.parent = mci_pdev;
943-
mci->dev.bus = mci->bus;
944922
mci->dev.groups = groups;
945923
dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
946924
dev_set_drvdata(&mci->dev, mci);
@@ -950,7 +928,7 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci,
950928
err = device_add(&mci->dev);
951929
if (err < 0) {
952930
edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev));
953-
goto fail_unregister_bus;
931+
goto out;
954932
}
955933

956934
/*
@@ -998,10 +976,8 @@ int edac_create_sysfs_mci_device(struct mem_ctl_info *mci,
998976
device_unregister(&dimm->dev);
999977
}
1000978
device_unregister(&mci->dev);
1001-
fail_unregister_bus:
1002-
bus_unregister(mci->bus);
1003-
kfree(name);
1004979

980+
out:
1005981
return err;
1006982
}
1007983

@@ -1032,13 +1008,8 @@ void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
10321008

10331009
void edac_unregister_sysfs(struct mem_ctl_info *mci)
10341010
{
1035-
struct bus_type *bus = mci->bus;
1036-
const char *name = mci->bus->name;
1037-
10381011
edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
10391012
device_unregister(&mci->dev);
1040-
bus_unregister(bus);
1041-
kfree(name);
10421013
}
10431014

10441015
static void mc_attr_release(struct device *dev)

‎drivers/edac/fsl_ddr_edac.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
* Freescale Memory Controller kernel module
33
*
44
* Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
5-
* ARM-based Layerscape SoCs including LS2xxx. Originally split
6-
* out from mpc85xx_edac EDAC driver.
5+
* ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
6+
* split out from mpc85xx_edac EDAC driver.
77
*
88
* Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
99
*
@@ -51,6 +51,7 @@ static inline void ddr_out32(void __iomem *addr, u32 value)
5151
iowrite32be(value, addr);
5252
}
5353

54+
#ifdef CONFIG_EDAC_DEBUG
5455
/************************ MC SYSFS parts ***********************************/
5556

5657
#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
@@ -151,11 +152,14 @@ static DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
151152
fsl_mc_inject_data_lo_show, fsl_mc_inject_data_lo_store);
152153
static DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
153154
fsl_mc_inject_ctrl_show, fsl_mc_inject_ctrl_store);
155+
#endif /* CONFIG_EDAC_DEBUG */
154156

155157
static struct attribute *fsl_ddr_dev_attrs[] = {
158+
#ifdef CONFIG_EDAC_DEBUG
156159
&dev_attr_inject_data_hi.attr,
157160
&dev_attr_inject_data_lo.attr,
158161
&dev_attr_inject_ctrl.attr,
162+
#endif
159163
NULL
160164
};
161165

‎drivers/edac/fsl_ddr_edac.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
* Freescale Memory Controller kernel module
33
*
44
* Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
5-
* ARM-based Layerscape SoCs including LS2xxx. Originally split
6-
* out from mpc85xx_edac EDAC driver.
5+
* ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
6+
* split out from mpc85xx_edac EDAC driver.
77
*
88
* Author: Dave Jiang <djiang@mvista.com>
99
*

‎drivers/edac/i3000_edac.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -508,8 +508,8 @@ static int __init i3000_init(void)
508508

509509
edac_dbg(3, "MC:\n");
510510

511-
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
512-
opstate_init();
511+
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
512+
opstate_init();
513513

514514
pci_rc = pci_register_driver(&i3000_driver);
515515
if (pci_rc < 0)

‎drivers/edac/i5000_edac.c

Lines changed: 3 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1134,8 +1134,6 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
11341134
u32 actual_tolm;
11351135
u16 limit;
11361136
int slot_row;
1137-
int maxch;
1138-
int maxdimmperch;
11391137
int way0, way1;
11401138

11411139
pvt = mci->pvt_info;
@@ -1145,9 +1143,6 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
11451143
pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
11461144
&pvt->u.ambase_top);
11471145

1148-
maxdimmperch = pvt->maxdimmperch;
1149-
maxch = pvt->maxch;
1150-
11511146
edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
11521147
(long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
11531148

@@ -1253,16 +1248,14 @@ static int i5000_init_csrows(struct mem_ctl_info *mci)
12531248
{
12541249
struct i5000_pvt *pvt;
12551250
struct dimm_info *dimm;
1256-
int empty, channel_count;
1251+
int empty;
12571252
int max_csrows;
12581253
int mtr;
12591254
int csrow_megs;
12601255
int channel;
12611256
int slot;
12621257

12631258
pvt = mci->pvt_info;
1264-
1265-
channel_count = pvt->maxch;
12661259
max_csrows = pvt->maxdimmperch * 2;
12671260

12681261
empty = 1; /* Assume NO memory */
@@ -1559,8 +1552,8 @@ static int __init i5000_init(void)
15591552

15601553
edac_dbg(2, "MC:\n");
15611554

1562-
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
1563-
opstate_init();
1555+
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
1556+
opstate_init();
15641557

15651558
pci_rc = pci_register_driver(&i5000_driver);
15661559

‎drivers/edac/i7core_edac.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -724,7 +724,7 @@ static ssize_t i7core_inject_type_store(struct device *dev,
724724
const char *data, size_t count)
725725
{
726726
struct mem_ctl_info *mci = to_mci(dev);
727-
struct i7core_pvt *pvt = mci->pvt_info;
727+
struct i7core_pvt *pvt = mci->pvt_info;
728728
unsigned long value;
729729
int rc;
730730

‎drivers/edac/i82975x_edac.c

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ NOTE: Only ONE of the three must be enabled
104104
*
105105
* 31:14 Base Addr of 16K memory-mapped
106106
* configuration space
107-
* 13:1 reserverd
107+
* 13:1 reserved
108108
* 0 mem-mapped config space enable
109109
*/
110110

@@ -358,14 +358,6 @@ static int dual_channel_active(void __iomem *mch_window)
358358
return dualch;
359359
}
360360

361-
static enum dev_type i82975x_dram_type(void __iomem *mch_window, int rank)
362-
{
363-
/*
364-
* ECC is possible on i92975x ONLY with DEV_X8
365-
*/
366-
return DEV_X8;
367-
}
368-
369361
static void i82975x_init_csrows(struct mem_ctl_info *mci,
370362
struct pci_dev *pdev, void __iomem *mch_window)
371363
{
@@ -375,7 +367,6 @@ static void i82975x_init_csrows(struct mem_ctl_info *mci,
375367
u32 cumul_size, nr_pages;
376368
int index, chan;
377369
struct dimm_info *dimm;
378-
enum dev_type dtype;
379370

380371
last_cumul_size = 0;
381372

@@ -413,7 +404,6 @@ static void i82975x_init_csrows(struct mem_ctl_info *mci,
413404
* [0-7] for single-channel; i.e. csrow->nr_channels = 1
414405
* [0-3] for dual-channel; i.e. csrow->nr_channels = 2
415406
*/
416-
dtype = i82975x_dram_type(mch_window, index);
417407
for (chan = 0; chan < csrow->nr_channels; chan++) {
418408
dimm = mci->csrows[index]->channels[chan]->dimm;
419409

@@ -423,7 +413,10 @@ static void i82975x_init_csrows(struct mem_ctl_info *mci,
423413
(chan == 0) ? 'A' : 'B',
424414
index);
425415
dimm->grain = 1 << 7; /* 128Byte cache-line resolution */
426-
dimm->dtype = i82975x_dram_type(mch_window, index);
416+
417+
/* ECC is possible on i92975x ONLY with DEV_X8. */
418+
dimm->dtype = DEV_X8;
419+
427420
dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
428421
dimm->edac_mode = EDAC_SECDED; /* only supported */
429422
}
@@ -655,8 +648,8 @@ static int __init i82975x_init(void)
655648

656649
edac_dbg(3, "\n");
657650

658-
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
659-
opstate_init();
651+
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
652+
opstate_init();
660653

661654
pci_rc = pci_register_driver(&i82975x_driver);
662655
if (pci_rc < 0)

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