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Elad Razdavem330
Elad Raz
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davem330
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mlxsw: reg: Add Switch Port VID and Switch Port VLAN Membership registers definitions
Add SPVID and SPVM registers responsible for default port VID configuration and VLAN membership of a port. Signed-off-by: Elad Raz <eladr@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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  • drivers/net/ethernet/mellanox/mlxsw

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‎drivers/net/ethernet/mellanox/mlxsw/reg.h

Lines changed: 146 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -517,6 +517,148 @@ static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
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mlxsw_reg_spms_state_set(payload, vid, state);
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}
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/* SPVID - Switch Port VID
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* -----------------------
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* The switch port VID configures the default VID for a port.
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*/
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#define MLXSW_REG_SPVID_ID 0x200E
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#define MLXSW_REG_SPVID_LEN 0x08
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static const struct mlxsw_reg_info mlxsw_reg_spvid = {
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.id = MLXSW_REG_SPVID_ID,
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.len = MLXSW_REG_SPVID_LEN,
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};
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/* reg_spvid_local_port
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* Local port number.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
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/* reg_spvid_sub_port
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* Virtual port within the physical port.
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* Should be set to 0 when virtual ports are not enabled on the port.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
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/* reg_spvid_pvid
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* Port default VID
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* Access: RW
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*/
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MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
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static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
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{
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MLXSW_REG_ZERO(spvid, payload);
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mlxsw_reg_spvid_local_port_set(payload, local_port);
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mlxsw_reg_spvid_pvid_set(payload, pvid);
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}
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/* SPVM - Switch Port VLAN Membership
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* ----------------------------------
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* The Switch Port VLAN Membership register configures the VLAN membership
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* of a port in a VLAN denoted by VID. VLAN membership is managed per
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* virtual port. The register can be used to add and remove VID(s) from a port.
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*/
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#define MLXSW_REG_SPVM_ID 0x200F
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#define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
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#define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
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#define MLXSW_REG_SPVM_REC_MAX_COUNT 256
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#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
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MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
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static const struct mlxsw_reg_info mlxsw_reg_spvm = {
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.id = MLXSW_REG_SPVM_ID,
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.len = MLXSW_REG_SPVM_LEN,
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};
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/* reg_spvm_pt
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* Priority tagged. If this bit is set, packets forwarded to the port with
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* untagged VLAN membership (u bit is set) will be tagged with priority tag
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* (VID=0)
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* Access: RW
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*/
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MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
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/* reg_spvm_pte
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* Priority Tagged Update Enable. On Write operations, if this bit is cleared,
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* the pt bit will NOT be updated. To update the pt bit, pte must be set.
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* Access: WO
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*/
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MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
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/* reg_spvm_local_port
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* Local port number.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
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/* reg_spvm_sub_port
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* Virtual port within the physical port.
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* Should be set to 0 when virtual ports are not enabled on the port.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
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/* reg_spvm_num_rec
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* Number of records to update. Each record contains: i, e, u, vid.
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* Access: OP
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*/
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MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
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/* reg_spvm_rec_i
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* Ingress membership in VLAN ID.
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* Access: Index
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*/
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MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
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MLXSW_REG_SPVM_BASE_LEN, 14, 1,
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MLXSW_REG_SPVM_REC_LEN, 0, false);
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/* reg_spvm_rec_e
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* Egress membership in VLAN ID.
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* Access: Index
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*/
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MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
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MLXSW_REG_SPVM_BASE_LEN, 13, 1,
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MLXSW_REG_SPVM_REC_LEN, 0, false);
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/* reg_spvm_rec_u
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* Untagged - port is an untagged member - egress transmission uses untagged
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* frames on VID<n>
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* Access: Index
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*/
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MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
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MLXSW_REG_SPVM_BASE_LEN, 12, 1,
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MLXSW_REG_SPVM_REC_LEN, 0, false);
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/* reg_spvm_rec_vid
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* Egress membership in VLAN ID.
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* Access: Index
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*/
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MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
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MLXSW_REG_SPVM_BASE_LEN, 0, 12,
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MLXSW_REG_SPVM_REC_LEN, 0, false);
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static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
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u16 vid_begin, u16 vid_end,
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bool is_member, bool untagged)
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{
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int size = vid_end - vid_begin + 1;
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int i;
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MLXSW_REG_ZERO(spvm, payload);
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mlxsw_reg_spvm_local_port_set(payload, local_port);
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mlxsw_reg_spvm_num_rec_set(payload, size);
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for (i = 0; i < size; i++) {
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mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
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mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
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mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
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mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
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}
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}
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/* SFGC - Switch Flooding Group Configuration
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* ------------------------------------------
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* The following register controls the association of flooding tables and MIDs
@@ -1570,6 +1712,10 @@ static inline const char *mlxsw_reg_id_str(u16 reg_id)
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return "SFN";
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case MLXSW_REG_SPMS_ID:
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return "SPMS";
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case MLXSW_REG_SPVID_ID:
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return "SPVID";
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case MLXSW_REG_SPVM_ID:
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return "SPVM";
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case MLXSW_REG_SFGC_ID:
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return "SFGC";
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case MLXSW_REG_SFTR_ID:

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