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torvaldstorvalds
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Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 cpufeature updates from Thomas Gleixner: - a workaround for the MONITOR instruction erratum of Goldmont CPUs - small fixes and cleanups here and there * 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpu: Add workaround for MONITOR instruction erratum on Goldmont based CPUs x86/cpu: Rename "WESTMERE2" family to "NEHALEM_G" x86/amd_nb: Clean up init path x86/cpufeature: Add helper macro for mask check macros x86/cpufeature: Make sure DISABLED/REQUIRED macros are updated x86/cpufeature: Update cpufeaure macros
2 parents 7f7d556 + 08e237f commit b325e04

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11 files changed

+83
-67
lines changed

11 files changed

+83
-67
lines changed

‎arch/x86/events/msr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,11 +36,11 @@ static bool test_intel(int idx)
3636

3737
switch (boot_cpu_data.x86_model) {
3838
case INTEL_FAM6_NEHALEM:
39+
case INTEL_FAM6_NEHALEM_G:
3940
case INTEL_FAM6_NEHALEM_EP:
4041
case INTEL_FAM6_NEHALEM_EX:
4142

4243
case INTEL_FAM6_WESTMERE:
43-
case INTEL_FAM6_WESTMERE2:
4444
case INTEL_FAM6_WESTMERE_EP:
4545
case INTEL_FAM6_WESTMERE_EX:
4646

‎arch/x86/include/asm/cpufeature.h

Lines changed: 53 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -49,43 +49,59 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
4949
#define test_cpu_cap(c, bit) \
5050
test_bit(bit, (unsigned long *)((c)->x86_capability))
5151

52-
#define REQUIRED_MASK_BIT_SET(bit) \
53-
( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0 )) || \
54-
(((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1 )) || \
55-
(((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2 )) || \
56-
(((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3 )) || \
57-
(((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4 )) || \
58-
(((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5 )) || \
59-
(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6 )) || \
60-
(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7 )) || \
61-
(((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8 )) || \
62-
(((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9 )) || \
63-
(((bit)>>5)==10 && (1UL<<((bit)&31) & REQUIRED_MASK10)) || \
64-
(((bit)>>5)==11 && (1UL<<((bit)&31) & REQUIRED_MASK11)) || \
65-
(((bit)>>5)==12 && (1UL<<((bit)&31) & REQUIRED_MASK12)) || \
66-
(((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) || \
67-
(((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK14)) || \
68-
(((bit)>>5)==15 && (1UL<<((bit)&31) & REQUIRED_MASK15)) || \
69-
(((bit)>>5)==16 && (1UL<<((bit)&31) & REQUIRED_MASK16)) )
70-
71-
#define DISABLED_MASK_BIT_SET(bit) \
72-
( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0 )) || \
73-
(((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1 )) || \
74-
(((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2 )) || \
75-
(((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3 )) || \
76-
(((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4 )) || \
77-
(((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5 )) || \
78-
(((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6 )) || \
79-
(((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7 )) || \
80-
(((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8 )) || \
81-
(((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9 )) || \
82-
(((bit)>>5)==10 && (1UL<<((bit)&31) & DISABLED_MASK10)) || \
83-
(((bit)>>5)==11 && (1UL<<((bit)&31) & DISABLED_MASK11)) || \
84-
(((bit)>>5)==12 && (1UL<<((bit)&31) & DISABLED_MASK12)) || \
85-
(((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) || \
86-
(((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK14)) || \
87-
(((bit)>>5)==15 && (1UL<<((bit)&31) & DISABLED_MASK15)) || \
88-
(((bit)>>5)==16 && (1UL<<((bit)&31) & DISABLED_MASK16)) )
52+
/*
53+
* There are 32 bits/features in each mask word. The high bits
54+
* (selected with (bit>>5) give us the word number and the low 5
55+
* bits give us the bit/feature number inside the word.
56+
* (1UL<<((bit)&31) gives us a mask for the feature_bit so we can
57+
* see if it is set in the mask word.
58+
*/
59+
#define CHECK_BIT_IN_MASK_WORD(maskname, word, bit) \
60+
(((bit)>>5)==(word) && (1UL<<((bit)&31) & maskname##word ))
61+
62+
#define REQUIRED_MASK_BIT_SET(feature_bit) \
63+
( CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 0, feature_bit) || \
64+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 1, feature_bit) || \
65+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 2, feature_bit) || \
66+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 3, feature_bit) || \
67+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 4, feature_bit) || \
68+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 5, feature_bit) || \
69+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 6, feature_bit) || \
70+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 7, feature_bit) || \
71+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 8, feature_bit) || \
72+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 9, feature_bit) || \
73+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 10, feature_bit) || \
74+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 11, feature_bit) || \
75+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 12, feature_bit) || \
76+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 13, feature_bit) || \
77+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 14, feature_bit) || \
78+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \
79+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \
80+
CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \
81+
REQUIRED_MASK_CHECK || \
82+
BUILD_BUG_ON_ZERO(NCAPINTS != 18))
83+
84+
#define DISABLED_MASK_BIT_SET(feature_bit) \
85+
( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
86+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 1, feature_bit) || \
87+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 2, feature_bit) || \
88+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 3, feature_bit) || \
89+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 4, feature_bit) || \
90+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 5, feature_bit) || \
91+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 6, feature_bit) || \
92+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 7, feature_bit) || \
93+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 8, feature_bit) || \
94+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 9, feature_bit) || \
95+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 10, feature_bit) || \
96+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 11, feature_bit) || \
97+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 12, feature_bit) || \
98+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 13, feature_bit) || \
99+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 14, feature_bit) || \
100+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \
101+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \
102+
CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \
103+
DISABLED_MASK_CHECK || \
104+
BUILD_BUG_ON_ZERO(NCAPINTS != 18))
89105

90106
#define cpu_has(c, bit) \
91107
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \

‎arch/x86/include/asm/cpufeatures.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -309,5 +309,5 @@
309309
#endif
310310
#define X86_BUG_NULL_SEG X86_BUG(10) /* Nulling a selector preserves the base */
311311
#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */
312-
312+
#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
313313
#endif /* _ASM_X86_CPUFEATURES_H */

‎arch/x86/include/asm/disabled-features.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,5 +56,7 @@
5656
#define DISABLED_MASK14 0
5757
#define DISABLED_MASK15 0
5858
#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE)
59+
#define DISABLED_MASK17 0
60+
#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
5961

6062
#endif /* _ASM_X86_DISABLED_FEATURES_H */

‎arch/x86/include/asm/intel-family.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
* "Extreme" ones, like Broadwell-E.
99
*
1010
* Things ending in "2" are usually because we have no better
11-
* name for them. There's no processor called "WESTMERE2".
11+
* name for them. There's no processor called "SILVERMONT2".
1212
*/
1313

1414
#define INTEL_FAM6_CORE_YONAH 0x0E
@@ -18,10 +18,10 @@
1818
#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
1919

2020
#define INTEL_FAM6_NEHALEM 0x1E
21+
#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
2122
#define INTEL_FAM6_NEHALEM_EP 0x1A
2223
#define INTEL_FAM6_NEHALEM_EX 0x2E
2324
#define INTEL_FAM6_WESTMERE 0x25
24-
#define INTEL_FAM6_WESTMERE2 0x1F
2525
#define INTEL_FAM6_WESTMERE_EP 0x2C
2626
#define INTEL_FAM6_WESTMERE_EX 0x2F
2727

‎arch/x86/include/asm/mwait.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
9797
*/
9898
static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
9999
{
100-
if (!current_set_polling_and_test()) {
100+
if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) {
101101
if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) {
102102
mb();
103103
clflush((void *)&current_thread_info()->flags);

‎arch/x86/include/asm/required-features.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -99,5 +99,7 @@
9999
#define REQUIRED_MASK14 0
100100
#define REQUIRED_MASK15 0
101101
#define REQUIRED_MASK16 0
102+
#define REQUIRED_MASK17 0
103+
#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)
102104

103105
#endif /* _ASM_X86_REQUIRED_FEATURES_H */

‎arch/x86/kernel/amd_nb.c

Lines changed: 14 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -219,24 +219,22 @@ int amd_set_subcaches(int cpu, unsigned long mask)
219219
return 0;
220220
}
221221

222-
static int amd_cache_gart(void)
222+
static void amd_cache_gart(void)
223223
{
224224
u16 i;
225225

226-
if (!amd_nb_has_feature(AMD_NB_GART))
227-
return 0;
228-
229-
flush_words = kmalloc(amd_nb_num() * sizeof(u32), GFP_KERNEL);
230-
if (!flush_words) {
231-
amd_northbridges.flags &= ~AMD_NB_GART;
232-
return -ENOMEM;
233-
}
226+
if (!amd_nb_has_feature(AMD_NB_GART))
227+
return;
234228

235-
for (i = 0; i != amd_nb_num(); i++)
236-
pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c,
237-
&flush_words[i]);
229+
flush_words = kmalloc(amd_nb_num() * sizeof(u32), GFP_KERNEL);
230+
if (!flush_words) {
231+
amd_northbridges.flags &= ~AMD_NB_GART;
232+
pr_notice("Cannot initialize GART flush words, GART support disabled\n");
233+
return;
234+
}
238235

239-
return 0;
236+
for (i = 0; i != amd_nb_num(); i++)
237+
pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
240238
}
241239

242240
void amd_flush_garts(void)
@@ -278,17 +276,10 @@ EXPORT_SYMBOL_GPL(amd_flush_garts);
278276

279277
static __init int init_amd_nbs(void)
280278
{
281-
int err = 0;
279+
amd_cache_northbridges();
280+
amd_cache_gart();
282281

283-
err = amd_cache_northbridges();
284-
285-
if (err < 0)
286-
pr_notice("Cannot enumerate AMD northbridges\n");
287-
288-
if (amd_cache_gart() < 0)
289-
pr_notice("Cannot initialize GART flush words, GART support disabled\n");
290-
291-
return err;
282+
return 0;
292283
}
293284

294285
/* This has to go after the PCI subsystem */

‎arch/x86/kernel/cpu/intel.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@
1313
#include <asm/msr.h>
1414
#include <asm/bugs.h>
1515
#include <asm/cpu.h>
16+
#include <asm/intel-family.h>
1617

1718
#ifdef CONFIG_X86_64
1819
#include <linux/topology.h>
@@ -508,6 +509,10 @@ static void init_intel(struct cpuinfo_x86 *c)
508509
(c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
509510
set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
510511

512+
if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
513+
((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
514+
set_cpu_bug(c, X86_BUG_MONITOR);
515+
511516
#ifdef CONFIG_X86_64
512517
if (c->x86 == 15)
513518
c->x86_cache_alignment = c->x86_clflush_size * 2;

‎arch/x86/kernel/process.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -404,7 +404,7 @@ static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
404404
if (c->x86_vendor != X86_VENDOR_INTEL)
405405
return 0;
406406

407-
if (!cpu_has(c, X86_FEATURE_MWAIT))
407+
if (!cpu_has(c, X86_FEATURE_MWAIT) || static_cpu_has_bug(X86_BUG_MONITOR))
408408
return 0;
409409

410410
return 1;

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