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Jasper Mattssonbebarino
Jasper Mattsson
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bebarino
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clk: mediatek: Mark bus and DRAM related clocks as critical
Currently, DRAM-related clocks are not marked with CLK_IS_CRITICAL for MT6797. This causes memory corruption when the system is booted without clk_ignore_unused. This patch marks MUX ddrphycfg_sel as well as gates infra_dramc_f26m and infra_dramc_b_f26m as CLK_IS_CRITICAL. Signed-off-by: Jasper Mattsson <jasu@njomotys.info> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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‎drivers/clk/mediatek/clk-mt6797.c

Lines changed: 43 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -324,15 +324,19 @@ static const char * const anc_md32_parents[] = {
324324
"univpll_d5",
325325
};
326326

327+
/*
328+
* Clock mux ddrphycfg is needed by the DRAM controller. We mark it as
329+
* critical as otherwise the system will hang after boot.
330+
*/
327331
static const struct mtk_composite top_muxes[] = {
328332
MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE, "ulposc_axi_ck_mux_pre",
329333
ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
330334
MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
331335
ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
332336
MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
333337
0x0040, 0, 2),
334-
MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
335-
0x0040, 16, 2),
338+
MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
339+
0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
336340
MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
337341
0x0040, 24, 2),
338342
MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
@@ -424,33 +428,45 @@ static const struct mtk_gate_regs infra2_cg_regs = {
424428
.sta_ofs = 0x00b0,
425429
};
426430

427-
#define GATE_ICG0(_id, _name, _parent, _shift) { \
428-
.id = _id, \
429-
.name = _name, \
430-
.parent_name = _parent, \
431-
.regs = &infra0_cg_regs, \
432-
.shift = _shift, \
433-
.ops = &mtk_clk_gate_ops_setclr, \
431+
#define GATE_ICG0(_id, _name, _parent, _shift) { \
432+
.id = _id, \
433+
.name = _name, \
434+
.parent_name = _parent, \
435+
.regs = &infra0_cg_regs, \
436+
.shift = _shift, \
437+
.ops = &mtk_clk_gate_ops_setclr, \
434438
}
435439

436-
#define GATE_ICG1(_id, _name, _parent, _shift) { \
437-
.id = _id, \
438-
.name = _name, \
439-
.parent_name = _parent, \
440-
.regs = &infra1_cg_regs, \
441-
.shift = _shift, \
442-
.ops = &mtk_clk_gate_ops_setclr, \
440+
#define GATE_ICG1(_id, _name, _parent, _shift) \
441+
GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
442+
443+
#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \
444+
.id = _id, \
445+
.name = _name, \
446+
.parent_name = _parent, \
447+
.regs = &infra1_cg_regs, \
448+
.shift = _shift, \
449+
.ops = &mtk_clk_gate_ops_setclr, \
450+
.flags = _flags, \
443451
}
444452

445-
#define GATE_ICG2(_id, _name, _parent, _shift) { \
446-
.id = _id, \
447-
.name = _name, \
448-
.parent_name = _parent, \
449-
.regs = &infra2_cg_regs, \
450-
.shift = _shift, \
451-
.ops = &mtk_clk_gate_ops_setclr, \
453+
#define GATE_ICG2(_id, _name, _parent, _shift) \
454+
GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
455+
456+
#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \
457+
.id = _id, \
458+
.name = _name, \
459+
.parent_name = _parent, \
460+
.regs = &infra2_cg_regs, \
461+
.shift = _shift, \
462+
.ops = &mtk_clk_gate_ops_setclr, \
463+
.flags = _flags, \
452464
}
453465

466+
/*
467+
* Clock gates dramc and dramc_b are needed by the DRAM controller.
468+
* We mark them as critical as otherwise the system will hang after boot.
469+
*/
454470
static const struct mtk_gate infra_clks[] = {
455471
GATE_ICG0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "ulposc", 0),
456472
GATE_ICG0(CLK_INFRA_PMIC_AP, "infra_pmic_ap", "pmicspi_sel", 1),
@@ -505,7 +521,8 @@ static const struct mtk_gate infra_clks[] = {
505521
GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
506522
GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
507523
GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
508-
GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
524+
GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
525+
"clk26m", 31, CLK_IS_CRITICAL),
509526
GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
510527
GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
511528
GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
@@ -516,7 +533,8 @@ static const struct mtk_gate infra_clks[] = {
516533
GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
517534
GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
518535
GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
519-
GATE_ICG2(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", "clk26m", 11),
536+
GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
537+
"clk26m", 11, CLK_IS_CRITICAL),
520538
GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
521539
GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
522540
GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),

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