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davem330davem330
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Merge branch 'amd-xgbe-next'
Tom Lendacky says: ==================== amd-xgbe: AMD XGBE driver updates 2015-03-19 The following series of patches includes functional updates and changes to the driver. - Use the phydev->advertising field instead of the phydev->supported field when configuring for auto-negotiation, etc. - Use the phy_driver flags field for setting the transceiver type instead of hardcoding it in the ethtool support. - Provide an auto-negotiation timeout check - Clarify the Tx/Rx queue information messages - Use the new DMA memory barrier operations - Set the device DMA mask based on what the hardware reports - Remove the software implementation of Tx coalescing - Fix the reporting of the Rx coalescing value - Use napi_alloc_skb when allocating an SKB in softirq This patch series is based on net-next. Changes from v2: - Use jiffies instead of timespec for the auto-negotiation timeout check - Remove the Rx path SKB allocation re-work patch since we should only inline the headers and the current code guards better against any hardware bugs Changes from v1: - Default to 32-bit DMA width (minimum supported) if hardware returns an unexpected DMA width value ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2 parents ebd6af0 + 385565a commit b4c11cb

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7 files changed

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lines changed

7 files changed

+127
-90
lines changed

‎drivers/net/ethernet/amd/xgbe/xgbe-common.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -365,6 +365,8 @@
365365
#define MAC_HWF0R_TXCOESEL_WIDTH 1
366366
#define MAC_HWF0R_VLHASH_INDEX 4
367367
#define MAC_HWF0R_VLHASH_WIDTH 1
368+
#define MAC_HWF1R_ADDR64_INDEX 14
369+
#define MAC_HWF1R_ADDR64_WIDTH 2
368370
#define MAC_HWF1R_ADVTHWORD_INDEX 13
369371
#define MAC_HWF1R_ADVTHWORD_WIDTH 1
370372
#define MAC_HWF1R_DBGMEMA_INDEX 19

‎drivers/net/ethernet/amd/xgbe/xgbe-dev.c

Lines changed: 16 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1068,7 +1068,7 @@ static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
10681068
rdesc->desc3 = 0;
10691069

10701070
/* Make sure ownership is written to the descriptor */
1071-
wmb();
1071+
dma_wmb();
10721072
}
10731073

10741074
static void xgbe_tx_desc_init(struct xgbe_channel *channel)
@@ -1124,12 +1124,12 @@ static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata)
11241124
* is written to the descriptor(s) before setting the OWN bit
11251125
* for the descriptor
11261126
*/
1127-
wmb();
1127+
dma_wmb();
11281128

11291129
XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
11301130

11311131
/* Make sure ownership is written to the descriptor */
1132-
wmb();
1132+
dma_wmb();
11331133
}
11341134

11351135
static void xgbe_rx_desc_init(struct xgbe_channel *channel)
@@ -1358,18 +1358,20 @@ static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
13581358
struct xgbe_prv_data *pdata = channel->pdata;
13591359
struct xgbe_ring_data *rdata;
13601360

1361+
/* Make sure everything is written before the register write */
1362+
wmb();
1363+
13611364
/* Issue a poll command to Tx DMA by writing address
13621365
* of next immediate free descriptor */
13631366
rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
13641367
XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
13651368
lower_32_bits(rdata->rdesc_dma));
13661369

1367-
/* Start the Tx coalescing timer */
1370+
/* Start the Tx timer */
13681371
if (pdata->tx_usecs && !channel->tx_timer_active) {
13691372
channel->tx_timer_active = 1;
1370-
hrtimer_start(&channel->tx_timer,
1371-
ktime_set(0, pdata->tx_usecs * NSEC_PER_USEC),
1372-
HRTIMER_MODE_REL);
1373+
mod_timer(&channel->tx_timer,
1374+
jiffies + usecs_to_jiffies(pdata->tx_usecs));
13731375
}
13741376

13751377
ring->tx.xmit_more = 0;
@@ -1565,7 +1567,7 @@ static void xgbe_dev_xmit(struct xgbe_channel *channel)
15651567
* is written to the descriptor(s) before setting the OWN bit
15661568
* for the first descriptor
15671569
*/
1568-
wmb();
1570+
dma_wmb();
15691571

15701572
/* Set OWN bit for the first descriptor */
15711573
rdata = XGBE_GET_DESC_DATA(ring, start_index);
@@ -1577,7 +1579,7 @@ static void xgbe_dev_xmit(struct xgbe_channel *channel)
15771579
#endif
15781580

15791581
/* Make sure ownership is written to the descriptor */
1580-
wmb();
1582+
dma_wmb();
15811583

15821584
ring->cur = cur_index + 1;
15831585
if (!packet->skb->xmit_more ||
@@ -1613,7 +1615,7 @@ static int xgbe_dev_read(struct xgbe_channel *channel)
16131615
return 1;
16141616

16151617
/* Make sure descriptor fields are read after reading the OWN bit */
1616-
rmb();
1618+
dma_rmb();
16171619

16181620
#ifdef XGMAC_ENABLE_RX_DESC_DUMP
16191621
xgbe_dump_rx_desc(ring, rdesc, ring->cur);
@@ -2004,7 +2006,8 @@ static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
20042006
for (i = 0; i < pdata->tx_q_count; i++)
20052007
XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
20062008

2007-
netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n",
2009+
netdev_notice(pdata->netdev,
2010+
"%d Tx hardware queues, %d byte fifo per queue\n",
20082011
pdata->tx_q_count, ((fifo_size + 1) * 256));
20092012
}
20102013

@@ -2019,7 +2022,8 @@ static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
20192022
for (i = 0; i < pdata->rx_q_count; i++)
20202023
XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
20212024

2022-
netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n",
2025+
netdev_notice(pdata->netdev,
2026+
"%d Rx hardware queues, %d byte fifo per queue\n",
20232027
pdata->rx_q_count, ((fifo_size + 1) * 256));
20242028
}
20252029

‎drivers/net/ethernet/amd/xgbe/xgbe-drv.c

Lines changed: 29 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -411,11 +411,9 @@ static irqreturn_t xgbe_dma_isr(int irq, void *data)
411411
return IRQ_HANDLED;
412412
}
413413

414-
static enum hrtimer_restart xgbe_tx_timer(struct hrtimer *timer)
414+
static void xgbe_tx_timer(unsigned long data)
415415
{
416-
struct xgbe_channel *channel = container_of(timer,
417-
struct xgbe_channel,
418-
tx_timer);
416+
struct xgbe_channel *channel = (struct xgbe_channel *)data;
419417
struct xgbe_prv_data *pdata = channel->pdata;
420418
struct napi_struct *napi;
421419

@@ -437,8 +435,6 @@ static enum hrtimer_restart xgbe_tx_timer(struct hrtimer *timer)
437435
channel->tx_timer_active = 0;
438436

439437
DBGPR("<--xgbe_tx_timer\n");
440-
441-
return HRTIMER_NORESTART;
442438
}
443439

444440
static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata)
@@ -454,9 +450,8 @@ static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata)
454450
break;
455451

456452
DBGPR(" %s adding tx timer\n", channel->name);
457-
hrtimer_init(&channel->tx_timer, CLOCK_MONOTONIC,
458-
HRTIMER_MODE_REL);
459-
channel->tx_timer.function = xgbe_tx_timer;
453+
setup_timer(&channel->tx_timer, xgbe_tx_timer,
454+
(unsigned long)channel);
460455
}
461456

462457
DBGPR("<--xgbe_init_tx_timers\n");
@@ -475,8 +470,7 @@ static void xgbe_stop_tx_timers(struct xgbe_prv_data *pdata)
475470
break;
476471

477472
DBGPR(" %s deleting tx timer\n", channel->name);
478-
channel->tx_timer_active = 0;
479-
hrtimer_cancel(&channel->tx_timer);
473+
del_timer_sync(&channel->tx_timer);
480474
}
481475

482476
DBGPR("<--xgbe_stop_tx_timers\n");
@@ -519,6 +513,7 @@ void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
519513
RXFIFOSIZE);
520514
hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
521515
TXFIFOSIZE);
516+
hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
522517
hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
523518
hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
524519
hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
@@ -553,6 +548,21 @@ void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
553548
break;
554549
}
555550

551+
/* Translate the address width setting into actual number */
552+
switch (hw_feat->dma_width) {
553+
case 0:
554+
hw_feat->dma_width = 32;
555+
break;
556+
case 1:
557+
hw_feat->dma_width = 40;
558+
break;
559+
case 2:
560+
hw_feat->dma_width = 48;
561+
break;
562+
default:
563+
hw_feat->dma_width = 32;
564+
}
565+
556566
/* The Queue, Channel and TC counts are zero based so increment them
557567
* to get the actual number
558568
*/
@@ -692,6 +702,7 @@ void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
692702
DBGPR("-->xgbe_init_rx_coalesce\n");
693703

694704
pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
705+
pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
695706
pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
696707

697708
hw_if->config_rx_coalesce(pdata);
@@ -1800,23 +1811,25 @@ static void xgbe_rx_refresh(struct xgbe_channel *channel)
18001811
ring->dirty++;
18011812
}
18021813

1814+
/* Make sure everything is written before the register write */
1815+
wmb();
1816+
18031817
/* Update the Rx Tail Pointer Register with address of
18041818
* the last cleaned entry */
18051819
rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
18061820
XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
18071821
lower_32_bits(rdata->rdesc_dma));
18081822
}
18091823

1810-
static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
1824+
static struct sk_buff *xgbe_create_skb(struct napi_struct *napi,
18111825
struct xgbe_ring_data *rdata,
18121826
unsigned int *len)
18131827
{
1814-
struct net_device *netdev = pdata->netdev;
18151828
struct sk_buff *skb;
18161829
u8 *packet;
18171830
unsigned int copy_len;
18181831

1819-
skb = netdev_alloc_skb_ip_align(netdev, rdata->rx.hdr.dma_len);
1832+
skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len);
18201833
if (!skb)
18211834
return NULL;
18221835

@@ -1863,7 +1876,7 @@ static int xgbe_tx_poll(struct xgbe_channel *channel)
18631876

18641877
/* Make sure descriptor fields are read after reading the OWN
18651878
* bit */
1866-
rmb();
1879+
dma_rmb();
18671880

18681881
#ifdef XGMAC_ENABLE_TX_DESC_DUMP
18691882
xgbe_dump_tx_desc(ring, ring->dirty, 1, 0);
@@ -1986,7 +1999,7 @@ static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
19861999
rdata->rx.hdr.dma_len,
19872000
DMA_FROM_DEVICE);
19882001

1989-
skb = xgbe_create_skb(pdata, rdata, &put_len);
2002+
skb = xgbe_create_skb(napi, rdata, &put_len);
19902003
if (!skb) {
19912004
error = 1;
19922005
goto skip_data;

‎drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -291,7 +291,6 @@ static int xgbe_get_settings(struct net_device *netdev,
291291
return -ENODEV;
292292

293293
ret = phy_ethtool_gset(pdata->phydev, cmd);
294-
cmd->transceiver = XCVR_EXTERNAL;
295294

296295
DBGPR("<--xgbe_get_settings\n");
297296

@@ -378,18 +377,14 @@ static int xgbe_get_coalesce(struct net_device *netdev,
378377
struct ethtool_coalesce *ec)
379378
{
380379
struct xgbe_prv_data *pdata = netdev_priv(netdev);
381-
struct xgbe_hw_if *hw_if = &pdata->hw_if;
382-
unsigned int riwt;
383380

384381
DBGPR("-->xgbe_get_coalesce\n");
385382

386383
memset(ec, 0, sizeof(struct ethtool_coalesce));
387384

388-
riwt = pdata->rx_riwt;
389-
ec->rx_coalesce_usecs = hw_if->riwt_to_usec(pdata, riwt);
385+
ec->rx_coalesce_usecs = pdata->rx_usecs;
390386
ec->rx_max_coalesced_frames = pdata->rx_frames;
391387

392-
ec->tx_coalesce_usecs = pdata->tx_usecs;
393388
ec->tx_max_coalesced_frames = pdata->tx_frames;
394389

395390
DBGPR("<--xgbe_get_coalesce\n");
@@ -403,13 +398,14 @@ static int xgbe_set_coalesce(struct net_device *netdev,
403398
struct xgbe_prv_data *pdata = netdev_priv(netdev);
404399
struct xgbe_hw_if *hw_if = &pdata->hw_if;
405400
unsigned int rx_frames, rx_riwt, rx_usecs;
406-
unsigned int tx_frames, tx_usecs;
401+
unsigned int tx_frames;
407402

408403
DBGPR("-->xgbe_set_coalesce\n");
409404

410405
/* Check for not supported parameters */
411406
if ((ec->rx_coalesce_usecs_irq) ||
412407
(ec->rx_max_coalesced_frames_irq) ||
408+
(ec->tx_coalesce_usecs) ||
413409
(ec->tx_coalesce_usecs_irq) ||
414410
(ec->tx_max_coalesced_frames_irq) ||
415411
(ec->stats_block_coalesce_usecs) ||
@@ -439,17 +435,17 @@ static int xgbe_set_coalesce(struct net_device *netdev,
439435
}
440436

441437
rx_riwt = hw_if->usec_to_riwt(pdata, ec->rx_coalesce_usecs);
438+
rx_usecs = ec->rx_coalesce_usecs;
442439
rx_frames = ec->rx_max_coalesced_frames;
443440

444441
/* Use smallest possible value if conversion resulted in zero */
445-
if (ec->rx_coalesce_usecs && !rx_riwt)
442+
if (rx_usecs && !rx_riwt)
446443
rx_riwt = 1;
447444

448445
/* Check the bounds of values for Rx */
449446
if (rx_riwt > XGMAC_MAX_DMA_RIWT) {
450-
rx_usecs = hw_if->riwt_to_usec(pdata, XGMAC_MAX_DMA_RIWT);
451447
netdev_alert(netdev, "rx-usec is limited to %d usecs\n",
452-
rx_usecs);
448+
hw_if->riwt_to_usec(pdata, XGMAC_MAX_DMA_RIWT));
453449
return -EINVAL;
454450
}
455451
if (rx_frames > pdata->rx_desc_count) {
@@ -458,7 +454,6 @@ static int xgbe_set_coalesce(struct net_device *netdev,
458454
return -EINVAL;
459455
}
460456

461-
tx_usecs = ec->tx_coalesce_usecs;
462457
tx_frames = ec->tx_max_coalesced_frames;
463458

464459
/* Check the bounds of values for Tx */
@@ -469,10 +464,10 @@ static int xgbe_set_coalesce(struct net_device *netdev,
469464
}
470465

471466
pdata->rx_riwt = rx_riwt;
467+
pdata->rx_usecs = rx_usecs;
472468
pdata->rx_frames = rx_frames;
473469
hw_if->config_rx_coalesce(pdata);
474470

475-
pdata->tx_usecs = tx_usecs;
476471
pdata->tx_frames = tx_frames;
477472
hw_if->config_tx_coalesce(pdata);
478473

‎drivers/net/ethernet/amd/xgbe/xgbe-main.c

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -374,15 +374,6 @@ static int xgbe_probe(struct platform_device *pdev)
374374
pdata->awcache = XGBE_DMA_SYS_AWCACHE;
375375
}
376376

377-
/* Set the DMA mask */
378-
if (!dev->dma_mask)
379-
dev->dma_mask = &dev->coherent_dma_mask;
380-
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
381-
if (ret) {
382-
dev_err(dev, "dma_set_mask_and_coherent failed\n");
383-
goto err_io;
384-
}
385-
386377
/* Get the device interrupt */
387378
ret = platform_get_irq(pdev, 0);
388379
if (ret < 0) {
@@ -409,6 +400,16 @@ static int xgbe_probe(struct platform_device *pdev)
409400
/* Set default configuration data */
410401
xgbe_default_config(pdata);
411402

403+
/* Set the DMA mask */
404+
if (!dev->dma_mask)
405+
dev->dma_mask = &dev->coherent_dma_mask;
406+
ret = dma_set_mask_and_coherent(dev,
407+
DMA_BIT_MASK(pdata->hw_feat.dma_width));
408+
if (ret) {
409+
dev_err(dev, "dma_set_mask_and_coherent failed\n");
410+
goto err_io;
411+
}
412+
412413
/* Calculate the number of Tx and Rx rings to be created
413414
* -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
414415
* the number of Tx queues to the number of Tx channels

‎drivers/net/ethernet/amd/xgbe/xgbe.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@
222222
((_idx) & ((_ring)->rdesc_count - 1)))
223223

224224
/* Default coalescing parameters */
225-
#define XGMAC_INIT_DMA_TX_USECS 50
225+
#define XGMAC_INIT_DMA_TX_USECS 1000
226226
#define XGMAC_INIT_DMA_TX_FRAMES 25
227227

228228
#define XGMAC_MAX_DMA_RIWT 0xff
@@ -410,7 +410,7 @@ struct xgbe_channel {
410410
unsigned int saved_ier;
411411

412412
unsigned int tx_timer_active;
413-
struct hrtimer tx_timer;
413+
struct timer_list tx_timer;
414414

415415
struct xgbe_ring *tx_ring;
416416
struct xgbe_ring *rx_ring;
@@ -632,6 +632,7 @@ struct xgbe_hw_features {
632632
unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
633633
unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
634634
unsigned int adv_ts_hi; /* Advance Timestamping High Word */
635+
unsigned int dma_width; /* DMA width */
635636
unsigned int dcb; /* DCB Feature */
636637
unsigned int sph; /* Split Header Feature */
637638
unsigned int tso; /* TCP Segmentation Offload */
@@ -715,6 +716,7 @@ struct xgbe_prv_data {
715716

716717
/* Rx coalescing settings */
717718
unsigned int rx_riwt;
719+
unsigned int rx_usecs;
718720
unsigned int rx_frames;
719721

720722
/* Current Rx buffer size */

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