|
899 | 899 | ti,hwmods = "timer1";
|
900 | 900 | ti,timer-alwon;
|
901 | 901 | clock-names = "fck";
|
902 |
| - clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; |
| 902 | + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>; |
903 | 903 | };
|
904 | 904 |
|
905 | 905 | timer2: timer@48032000 {
|
|
1380 | 1380 | #address-cells = <1>;
|
1381 | 1381 | #size-cells = <0>;
|
1382 | 1382 | ti,hwmods = "qspi";
|
1383 |
| - clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>; |
| 1383 | + clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>; |
1384 | 1384 | clock-names = "fck";
|
1385 | 1385 | num-cs = <4>;
|
1386 | 1386 | interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
|
|
1403 | 1403 | reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
1404 | 1404 | syscon-phy-power = <&scm_conf 0x374>;
|
1405 | 1405 | clocks = <&sys_clkin1>,
|
1406 |
| - <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>; |
| 1406 | + <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; |
1407 | 1407 | clock-names = "sysclk", "refclk";
|
1408 | 1408 | syscon-pllreset = <&scm_conf 0x3fc>;
|
1409 | 1409 | #phy-cells = <0>;
|
|
1418 | 1418 | syscon-pcs = <&scm_conf_pcie 0x10>;
|
1419 | 1419 | clocks = <&dpll_pcie_ref_ck>,
|
1420 | 1420 | <&dpll_pcie_ref_m2ldo_ck>,
|
1421 |
| - <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>, |
1422 |
| - <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>, |
1423 |
| - <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>, |
| 1421 | + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>, |
| 1422 | + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>, |
| 1423 | + <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>, |
1424 | 1424 | <&optfclk_pciephy_div>,
|
1425 | 1425 | <&sys_clkin1>;
|
1426 | 1426 | clock-names = "dpll_ref", "dpll_ref_m2",
|
|
1438 | 1438 | syscon-pcs = <&scm_conf_pcie 0x10>;
|
1439 | 1439 | clocks = <&dpll_pcie_ref_ck>,
|
1440 | 1440 | <&dpll_pcie_ref_m2ldo_ck>,
|
1441 |
| - <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>, |
1442 |
| - <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>, |
1443 |
| - <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>, |
| 1441 | + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>, |
| 1442 | + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>, |
| 1443 | + <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>, |
1444 | 1444 | <&optfclk_pciephy_div>,
|
1445 | 1445 | <&sys_clkin1>;
|
1446 | 1446 | clock-names = "dpll_ref", "dpll_ref_m2",
|
|
1457 | 1457 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
1458 | 1458 | phys = <&sata_phy>;
|
1459 | 1459 | phy-names = "sata-phy";
|
1460 |
| - clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>; |
| 1460 | + clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>; |
1461 | 1461 | ti,hwmods = "sata";
|
1462 | 1462 | ports-implemented = <0x1>;
|
1463 | 1463 | };
|
|
1485 | 1485 | reg = <0x4a084000 0x400>;
|
1486 | 1486 | syscon-phy-power = <&scm_conf 0x300>;
|
1487 | 1487 | clocks = <&usb_phy1_always_on_clk32k>,
|
1488 |
| - <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>; |
| 1488 | + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; |
1489 | 1489 | clock-names = "wkupclk",
|
1490 | 1490 | "refclk";
|
1491 | 1491 | #phy-cells = <0>;
|
|
1497 | 1497 | reg = <0x4a085000 0x400>;
|
1498 | 1498 | syscon-phy-power = <&scm_conf 0xe74>;
|
1499 | 1499 | clocks = <&usb_phy2_always_on_clk32k>,
|
1500 |
| - <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>; |
| 1500 | + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>; |
1501 | 1501 | clock-names = "wkupclk",
|
1502 | 1502 | "refclk";
|
1503 | 1503 | #phy-cells = <0>;
|
|
1512 | 1512 | syscon-phy-power = <&scm_conf 0x370>;
|
1513 | 1513 | clocks = <&usb_phy3_always_on_clk32k>,
|
1514 | 1514 | <&sys_clkin1>,
|
1515 |
| - <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>; |
| 1515 | + <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>; |
1516 | 1516 | clock-names = "wkupclk",
|
1517 | 1517 | "sysclk",
|
1518 | 1518 | "refclk";
|
|
1530 | 1530 | <SYSC_IDLE_NO>,
|
1531 | 1531 | <SYSC_IDLE_SMART>,
|
1532 | 1532 | <SYSC_IDLE_SMART_WKUP>;
|
1533 |
| - clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>; |
| 1533 | + clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>; |
1534 | 1534 | clock-names = "fck";
|
1535 | 1535 | #address-cells = <1>;
|
1536 | 1536 | #size-cells = <1>;
|
|
1549 | 1549 | <SYSC_IDLE_NO>,
|
1550 | 1550 | <SYSC_IDLE_SMART>,
|
1551 | 1551 | <SYSC_IDLE_SMART_WKUP>;
|
1552 |
| - clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>; |
| 1552 | + clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>; |
1553 | 1553 | clock-names = "fck";
|
1554 | 1554 | #address-cells = <1>;
|
1555 | 1555 | #size-cells = <1>;
|
|
1672 | 1672 | ti,hwmods = "atl";
|
1673 | 1673 | ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
|
1674 | 1674 | <&atl_clkin2_ck>, <&atl_clkin3_ck>;
|
1675 |
| - clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; |
| 1675 | + clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>; |
1676 | 1676 | clock-names = "fck";
|
1677 | 1677 | status = "disabled";
|
1678 | 1678 | };
|
|
1688 | 1688 | interrupt-names = "tx", "rx";
|
1689 | 1689 | dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
|
1690 | 1690 | dma-names = "tx", "rx";
|
1691 |
| - clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>, |
1692 |
| - <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>; |
| 1691 | + clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, |
| 1692 | + <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; |
1693 | 1693 | clock-names = "fck", "ahclkx", "ahclkr";
|
1694 | 1694 | status = "disabled";
|
1695 | 1695 | };
|
|
1705 | 1705 | interrupt-names = "tx", "rx";
|
1706 | 1706 | dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
|
1707 | 1707 | dma-names = "tx", "rx";
|
1708 |
| - clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>, |
1709 |
| - <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>, |
1710 |
| - <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>; |
| 1708 | + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, |
| 1709 | + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, |
| 1710 | + <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; |
1711 | 1711 | clock-names = "fck", "ahclkx", "ahclkr";
|
1712 | 1712 | status = "disabled";
|
1713 | 1713 | };
|
|
1723 | 1723 | interrupt-names = "tx", "rx";
|
1724 | 1724 | dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
|
1725 | 1725 | dma-names = "tx", "rx";
|
1726 |
| - clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>, |
1727 |
| - <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; |
| 1726 | + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, |
| 1727 | + <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; |
1728 | 1728 | clock-names = "fck", "ahclkx";
|
1729 | 1729 | status = "disabled";
|
1730 | 1730 | };
|
|
1740 | 1740 | interrupt-names = "tx", "rx";
|
1741 | 1741 | dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
|
1742 | 1742 | dma-names = "tx", "rx";
|
1743 |
| - clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>, |
1744 |
| - <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>; |
| 1743 | + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, |
| 1744 | + <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; |
1745 | 1745 | clock-names = "fck", "ahclkx";
|
1746 | 1746 | status = "disabled";
|
1747 | 1747 | };
|
|
1757 | 1757 | interrupt-names = "tx", "rx";
|
1758 | 1758 | dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
|
1759 | 1759 | dma-names = "tx", "rx";
|
1760 |
| - clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>, |
1761 |
| - <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>; |
| 1760 | + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, |
| 1761 | + <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; |
1762 | 1762 | clock-names = "fck", "ahclkx";
|
1763 | 1763 | status = "disabled";
|
1764 | 1764 | };
|
|
1774 | 1774 | interrupt-names = "tx", "rx";
|
1775 | 1775 | dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
|
1776 | 1776 | dma-names = "tx", "rx";
|
1777 |
| - clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>, |
1778 |
| - <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>; |
| 1777 | + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, |
| 1778 | + <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; |
1779 | 1779 | clock-names = "fck", "ahclkx";
|
1780 | 1780 | status = "disabled";
|
1781 | 1781 | };
|
|
1791 | 1791 | interrupt-names = "tx", "rx";
|
1792 | 1792 | dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
|
1793 | 1793 | dma-names = "tx", "rx";
|
1794 |
| - clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>, |
1795 |
| - <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>; |
| 1794 | + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, |
| 1795 | + <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; |
1796 | 1796 | clock-names = "fck", "ahclkx";
|
1797 | 1797 | status = "disabled";
|
1798 | 1798 | };
|
|
1808 | 1808 | interrupt-names = "tx", "rx";
|
1809 | 1809 | dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
|
1810 | 1810 | dma-names = "tx", "rx";
|
1811 |
| - clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>, |
1812 |
| - <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>; |
| 1811 | + clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, |
| 1812 | + <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; |
1813 | 1813 | clock-names = "fck", "ahclkx";
|
1814 | 1814 | status = "disabled";
|
1815 | 1815 | };
|
|
1831 | 1831 | mac: ethernet@48484000 {
|
1832 | 1832 | compatible = "ti,dra7-cpsw","ti,cpsw";
|
1833 | 1833 | ti,hwmods = "gmac";
|
1834 |
| - clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>; |
| 1834 | + clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>; |
1835 | 1835 | clock-names = "fck", "cpts";
|
1836 | 1836 | cpdma_channels = <8>;
|
1837 | 1837 | ale_entries = <1024>;
|
|
1901 | 1901 | reg = <0x4ae3c000 0x2000>;
|
1902 | 1902 | syscon-raminit = <&scm_conf 0x558 0>;
|
1903 | 1903 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
1904 |
| - clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>; |
| 1904 | + clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>; |
1905 | 1905 | status = "disabled";
|
1906 | 1906 | };
|
1907 | 1907 |
|
|
1932 | 1932 | reg = <0x58001000 0x1000>;
|
1933 | 1933 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
1934 | 1934 | ti,hwmods = "dss_dispc";
|
1935 |
| - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; |
| 1935 | + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>; |
1936 | 1936 | clock-names = "fck";
|
1937 | 1937 | /* CTRL_CORE_SMA_SW_1 */
|
1938 | 1938 | syscon-pol = <&scm_conf 0x534>;
|
|
1948 | 1948 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
1949 | 1949 | status = "disabled";
|
1950 | 1950 | ti,hwmods = "dss_hdmi";
|
1951 |
| - clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, |
1952 |
| - <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>; |
| 1951 | + clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>, |
| 1952 | + <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>; |
1953 | 1953 | clock-names = "fck", "sys_clk";
|
1954 | 1954 | dmas = <&sdma_xbar 76>;
|
1955 | 1955 | dma-names = "audio_tx";
|
|
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