|
52 | 52 | /* Atmel chips */
|
53 | 53 | #define AT49BV640D 0x02de
|
54 | 54 | #define AT49BV640DT 0x02db
|
| 55 | +/* Sharp chips */ |
| 56 | +#define LH28F640BFHE_PTTL90 0x00b0 |
| 57 | +#define LH28F640BFHE_PBTL90 0x00b1 |
| 58 | +#define LH28F640BFHE_PTTL70A 0x00b2 |
| 59 | +#define LH28F640BFHE_PBTL70A 0x00b3 |
55 | 60 |
|
56 | 61 | static int cfi_intelext_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
|
57 | 62 | static int cfi_intelext_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
|
@@ -258,6 +263,36 @@ static void fixup_st_m28w320cb(struct mtd_info *mtd)
|
258 | 263 | (cfi->cfiq->EraseRegionInfo[1] & 0xffff0000) | 0x3e;
|
259 | 264 | };
|
260 | 265 |
|
| 266 | +static int is_LH28F640BF(struct cfi_private *cfi) |
| 267 | +{ |
| 268 | + /* Sharp LH28F640BF Family */ |
| 269 | + if (cfi->mfr == CFI_MFR_SHARP && ( |
| 270 | + cfi->id == LH28F640BFHE_PTTL90 || cfi->id == LH28F640BFHE_PBTL90 || |
| 271 | + cfi->id == LH28F640BFHE_PTTL70A || cfi->id == LH28F640BFHE_PBTL70A)) |
| 272 | + return 1; |
| 273 | + return 0; |
| 274 | +} |
| 275 | + |
| 276 | +static void fixup_LH28F640BF(struct mtd_info *mtd) |
| 277 | +{ |
| 278 | + struct map_info *map = mtd->priv; |
| 279 | + struct cfi_private *cfi = map->fldrv_priv; |
| 280 | + struct cfi_pri_intelext *extp = cfi->cmdset_priv; |
| 281 | + |
| 282 | + /* Reset the Partition Configuration Register on LH28F640BF |
| 283 | + * to a single partition (PCR = 0x000): PCR is embedded into A0-A15. */ |
| 284 | + if (is_LH28F640BF(cfi)) { |
| 285 | + printk(KERN_INFO "Reset Partition Config. Register: 1 Partition of 4 planes\n"); |
| 286 | + map_write(map, CMD(0x60), 0); |
| 287 | + map_write(map, CMD(0x04), 0); |
| 288 | + |
| 289 | + /* We have set one single partition thus |
| 290 | + * Simultaneous Operations are not allowed */ |
| 291 | + printk(KERN_INFO "cfi_cmdset_0001: Simultaneous Operations disabled\n"); |
| 292 | + extp->FeatureSupport &= ~512; |
| 293 | + } |
| 294 | +} |
| 295 | + |
261 | 296 | static void fixup_use_point(struct mtd_info *mtd)
|
262 | 297 | {
|
263 | 298 | struct map_info *map = mtd->priv;
|
@@ -309,6 +344,8 @@ static struct cfi_fixup cfi_fixup_table[] = {
|
309 | 344 | { CFI_MFR_ST, 0x00ba, /* M28W320CT */ fixup_st_m28w320ct },
|
310 | 345 | { CFI_MFR_ST, 0x00bb, /* M28W320CB */ fixup_st_m28w320cb },
|
311 | 346 | { CFI_MFR_INTEL, CFI_ID_ANY, fixup_unlock_powerup_lock },
|
| 347 | + { CFI_MFR_SHARP, CFI_ID_ANY, fixup_unlock_powerup_lock }, |
| 348 | + { CFI_MFR_SHARP, CFI_ID_ANY, fixup_LH28F640BF }, |
312 | 349 | { 0, 0, NULL }
|
313 | 350 | };
|
314 | 351 |
|
@@ -1649,6 +1686,12 @@ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
|
1649 | 1686 | initial_adr = adr;
|
1650 | 1687 | cmd_adr = adr & ~(wbufsize-1);
|
1651 | 1688 |
|
| 1689 | + /* Sharp LH28F640BF chips need the first address for the |
| 1690 | + * Page Buffer Program command. See Table 5 of |
| 1691 | + * LH28F320BF, LH28F640BF, LH28F128BF Series (Appendix FUM00701) */ |
| 1692 | + if (is_LH28F640BF(cfi)) |
| 1693 | + cmd_adr = adr; |
| 1694 | + |
1652 | 1695 | /* Let's determine this according to the interleave only once */
|
1653 | 1696 | write_cmd = (cfi->cfiq->P_ID != P_ID_INTEL_PERFORMANCE) ? CMD(0xe8) : CMD(0xe9);
|
1654 | 1697 |
|
|
0 commit comments