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torvaldstorvalds
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Merge tag 'pinctrl-v4.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull first round of pin control fixes from Linus Walleij: - a bunch of barnsjukdomar/kinderkrankheiten/maladie infantile in the Aspeed driver. (Why doesn't English have a word for this?) [ Maybe "teething problems" is the closest English idiom? - Linus T ] - fix a lockdep bug on the Intel BayTrail. - fix a few special laptop issues on the Intel pin controller solving suspend issues. * tag 'pinctrl-v4.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: intel: Only restore pins that are used by the driver pinctrl: baytrail: Fix lockdep pinctrl: aspeed-g5: Fix pin association of SPI1 function pinctrl: aspeed-g5: Fix GPIOE1 typo pinctrl: aspeed-g5: Fix names of GPID2 pins pinctrl: aspeed: "Not enabled" is a significant mux state
2 parents 8835ca5 + c538b94 commit b6ffb11

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5 files changed

+120
-24
lines changed

5 files changed

+120
-24
lines changed

‎Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,9 @@ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
4343

4444
GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
4545
I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
46-
RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8
46+
RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
47+
TIMER7 TIMER8 VGABIOSROM
48+
4749

4850
Examples:
4951

‎drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

Lines changed: 85 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -151,21 +151,21 @@ FUNC_GROUP_DECL(GPID0, F19, E21);
151151

152152
#define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
153153

154-
#define D20 26
154+
#define F20 26
155155
SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
156156
SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
157157
SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
158158
SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
159-
MS_PIN_DECL(D20, GPIOD2, SD2DAT0, GPID2IN);
159+
MS_PIN_DECL(F20, GPIOD2, SD2DAT0, GPID2IN);
160160

161-
#define D21 27
161+
#define D20 27
162162
SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
163163
SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
164164
SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
165165
SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
166-
MS_PIN_DECL(D21, GPIOD3, SD2DAT1, GPID2OUT);
166+
MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT);
167167

168-
FUNC_GROUP_DECL(GPID2, D20, D21);
168+
FUNC_GROUP_DECL(GPID2, F20, D20);
169169

170170
#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21)
171171
#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
@@ -182,28 +182,88 @@ SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
182182
SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
183183
SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
184184
SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
185-
MS_PIN_DECL(C20, GPIE0, NDCD3, GPIE0OUT);
185+
MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
186186

187187
FUNC_GROUP_DECL(GPIE0, B20, C20);
188188

189-
#define SPI1_DESC SIG_DESC_SET(HW_STRAP1, 13)
189+
#define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
190+
#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
191+
#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
192+
190193
#define C18 64
191-
SIG_EXPR_LIST_DECL_SINGLE(SYSCS, SPI1, COND1, SPI1_DESC);
194+
SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
195+
SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
196+
SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU);
192197
SS_PIN_DECL(C18, GPIOI0, SYSCS);
193198

194199
#define E15 65
195-
SIG_EXPR_LIST_DECL_SINGLE(SYSCK, SPI1, COND1, SPI1_DESC);
200+
SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
201+
SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
202+
SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU);
196203
SS_PIN_DECL(E15, GPIOI1, SYSCK);
197204

198-
#define A14 66
199-
SIG_EXPR_LIST_DECL_SINGLE(SYSMOSI, SPI1, COND1, SPI1_DESC);
200-
SS_PIN_DECL(A14, GPIOI2, SYSMOSI);
205+
#define B16 66
206+
SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
207+
SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
208+
SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
209+
SS_PIN_DECL(B16, GPIOI2, SYSMOSI);
201210

202211
#define C16 67
203-
SIG_EXPR_LIST_DECL_SINGLE(SYSMISO, SPI1, COND1, SPI1_DESC);
212+
SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
213+
SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
214+
SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
204215
SS_PIN_DECL(C16, GPIOI3, SYSMISO);
205216

206-
FUNC_GROUP_DECL(SPI1, C18, E15, A14, C16);
217+
#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
218+
219+
#define B15 68
220+
SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC);
221+
SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
222+
SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
223+
SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1),
224+
SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
225+
SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
226+
SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC);
227+
MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS);
228+
229+
#define C15 69
230+
SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC);
231+
SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
232+
SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
233+
SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1),
234+
SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
235+
SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
236+
SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC);
237+
MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK);
238+
239+
#define A14 70
240+
SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC);
241+
SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
242+
SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
243+
SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1),
244+
SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
245+
SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
246+
SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC);
247+
MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI);
248+
249+
#define A15 71
250+
SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC);
251+
SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
252+
SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
253+
SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1),
254+
SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
255+
SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
256+
SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC);
257+
MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
258+
259+
FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
260+
FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
261+
FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
262+
FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
263+
264+
#define R2 72
265+
SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
266+
SS_PIN_DECL(R2, GPIOJ0, SGPMCK);
207267

208268
#define L2 73
209269
SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
@@ -580,6 +640,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
580640
ASPEED_PINCTRL_PIN(A12),
581641
ASPEED_PINCTRL_PIN(A13),
582642
ASPEED_PINCTRL_PIN(A14),
643+
ASPEED_PINCTRL_PIN(A15),
583644
ASPEED_PINCTRL_PIN(A2),
584645
ASPEED_PINCTRL_PIN(A3),
585646
ASPEED_PINCTRL_PIN(A4),
@@ -592,6 +653,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
592653
ASPEED_PINCTRL_PIN(B12),
593654
ASPEED_PINCTRL_PIN(B13),
594655
ASPEED_PINCTRL_PIN(B14),
656+
ASPEED_PINCTRL_PIN(B15),
657+
ASPEED_PINCTRL_PIN(B16),
595658
ASPEED_PINCTRL_PIN(B2),
596659
ASPEED_PINCTRL_PIN(B20),
597660
ASPEED_PINCTRL_PIN(B3),
@@ -603,6 +666,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
603666
ASPEED_PINCTRL_PIN(C12),
604667
ASPEED_PINCTRL_PIN(C13),
605668
ASPEED_PINCTRL_PIN(C14),
669+
ASPEED_PINCTRL_PIN(C15),
606670
ASPEED_PINCTRL_PIN(C16),
607671
ASPEED_PINCTRL_PIN(C18),
608672
ASPEED_PINCTRL_PIN(C2),
@@ -614,7 +678,6 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
614678
ASPEED_PINCTRL_PIN(D10),
615679
ASPEED_PINCTRL_PIN(D2),
616680
ASPEED_PINCTRL_PIN(D20),
617-
ASPEED_PINCTRL_PIN(D21),
618681
ASPEED_PINCTRL_PIN(D4),
619682
ASPEED_PINCTRL_PIN(D5),
620683
ASPEED_PINCTRL_PIN(D6),
@@ -630,6 +693,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
630693
ASPEED_PINCTRL_PIN(E7),
631694
ASPEED_PINCTRL_PIN(E9),
632695
ASPEED_PINCTRL_PIN(F19),
696+
ASPEED_PINCTRL_PIN(F20),
633697
ASPEED_PINCTRL_PIN(F9),
634698
ASPEED_PINCTRL_PIN(H20),
635699
ASPEED_PINCTRL_PIN(L1),
@@ -691,11 +755,14 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
691755
ASPEED_PINCTRL_GROUP(RMII2),
692756
ASPEED_PINCTRL_GROUP(SD1),
693757
ASPEED_PINCTRL_GROUP(SPI1),
758+
ASPEED_PINCTRL_GROUP(SPI1DEBUG),
759+
ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
694760
ASPEED_PINCTRL_GROUP(TIMER4),
695761
ASPEED_PINCTRL_GROUP(TIMER5),
696762
ASPEED_PINCTRL_GROUP(TIMER6),
697763
ASPEED_PINCTRL_GROUP(TIMER7),
698764
ASPEED_PINCTRL_GROUP(TIMER8),
765+
ASPEED_PINCTRL_GROUP(VGABIOSROM),
699766
};
700767

701768
static const struct aspeed_pin_function aspeed_g5_functions[] = {
@@ -733,11 +800,14 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
733800
ASPEED_PINCTRL_FUNC(RMII2),
734801
ASPEED_PINCTRL_FUNC(SD1),
735802
ASPEED_PINCTRL_FUNC(SPI1),
803+
ASPEED_PINCTRL_FUNC(SPI1DEBUG),
804+
ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
736805
ASPEED_PINCTRL_FUNC(TIMER4),
737806
ASPEED_PINCTRL_FUNC(TIMER5),
738807
ASPEED_PINCTRL_FUNC(TIMER6),
739808
ASPEED_PINCTRL_FUNC(TIMER7),
740809
ASPEED_PINCTRL_FUNC(TIMER8),
810+
ASPEED_PINCTRL_FUNC(VGABIOSROM),
741811
};
742812

743813
static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {

‎drivers/pinctrl/aspeed/pinctrl-aspeed.c

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -166,13 +166,9 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
166166
bool enable, struct regmap *map)
167167
{
168168
int i;
169-
bool ret;
170-
171-
ret = aspeed_sig_expr_eval(expr, enable, map);
172-
if (ret)
173-
return ret;
174169

175170
for (i = 0; i < expr->ndescs; i++) {
171+
bool ret;
176172
const struct aspeed_sig_desc *desc = &expr->descs[i];
177173
u32 pattern = enable ? desc->enable : desc->disable;
178174

@@ -199,12 +195,18 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
199195
static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr,
200196
struct regmap *map)
201197
{
198+
if (aspeed_sig_expr_eval(expr, true, map))
199+
return true;
200+
202201
return aspeed_sig_expr_set(expr, true, map);
203202
}
204203

205204
static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr,
206205
struct regmap *map)
207206
{
207+
if (!aspeed_sig_expr_eval(expr, true, map))
208+
return true;
209+
208210
return aspeed_sig_expr_set(expr, false, map);
209211
}
210212

‎drivers/pinctrl/intel/pinctrl-baytrail.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1808,14 +1808,15 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
18081808
return PTR_ERR(vg->pctl_dev);
18091809
}
18101810

1811+
raw_spin_lock_init(&vg->lock);
1812+
18111813
ret = byt_gpio_probe(vg);
18121814
if (ret) {
18131815
pinctrl_unregister(vg->pctl_dev);
18141816
return ret;
18151817
}
18161818

18171819
platform_set_drvdata(pdev, vg);
1818-
raw_spin_lock_init(&vg->lock);
18191820
pm_runtime_enable(&pdev->dev);
18201821

18211822
return 0;

‎drivers/pinctrl/intel/pinctrl-intel.c

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include <linux/pinctrl/pinconf.h>
2020
#include <linux/pinctrl/pinconf-generic.h>
2121

22+
#include "../core.h"
2223
#include "pinctrl-intel.h"
2324

2425
/* Offset from regs */
@@ -1056,6 +1057,26 @@ int intel_pinctrl_remove(struct platform_device *pdev)
10561057
EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
10571058

10581059
#ifdef CONFIG_PM_SLEEP
1060+
static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1061+
{
1062+
const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1063+
1064+
if (!pd || !intel_pad_usable(pctrl, pin))
1065+
return false;
1066+
1067+
/*
1068+
* Only restore the pin if it is actually in use by the kernel (or
1069+
* by userspace). It is possible that some pins are used by the
1070+
* BIOS during resume and those are not always locked down so leave
1071+
* them alone.
1072+
*/
1073+
if (pd->mux_owner || pd->gpio_owner ||
1074+
gpiochip_line_is_irq(&pctrl->chip, pin))
1075+
return true;
1076+
1077+
return false;
1078+
}
1079+
10591080
int intel_pinctrl_suspend(struct device *dev)
10601081
{
10611082
struct platform_device *pdev = to_platform_device(dev);
@@ -1069,7 +1090,7 @@ int intel_pinctrl_suspend(struct device *dev)
10691090
const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
10701091
u32 val;
10711092

1072-
if (!intel_pad_usable(pctrl, desc->number))
1093+
if (!intel_pinctrl_should_save(pctrl, desc->number))
10731094
continue;
10741095

10751096
val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
@@ -1130,7 +1151,7 @@ int intel_pinctrl_resume(struct device *dev)
11301151
void __iomem *padcfg;
11311152
u32 val;
11321153

1133-
if (!intel_pad_usable(pctrl, desc->number))
1154+
if (!intel_pinctrl_should_save(pctrl, desc->number))
11341155
continue;
11351156

11361157
padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);

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