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oulijunjgunthorpe
oulijun
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jgunthorpe
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RDMA/hns: Refactor the codes for setting transport opode
Currently the transport opcodes which come from users configuration is set by similar code. This patch simplifies it. Signed-off-by: Lijun Ou <oulijun@huawei.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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‎drivers/infiniband/hw/hns/hns_roce_hw_v2.c

Lines changed: 18 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -191,6 +191,7 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp,
191191
int attr_mask;
192192
u32 tmp_len;
193193
int ret = 0;
194+
u32 hr_op;
194195
u8 *smac;
195196
int nreq;
196197
int i;
@@ -408,91 +409,60 @@ static int hns_roce_v2_post_send(struct ib_qp *ibqp,
408409

409410
switch (wr->opcode) {
410411
case IB_WR_RDMA_READ:
411-
roce_set_field(rc_sq_wqe->byte_4,
412-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
413-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
414-
HNS_ROCE_V2_WQE_OP_RDMA_READ);
412+
hr_op = HNS_ROCE_V2_WQE_OP_RDMA_READ;
415413
rc_sq_wqe->rkey =
416414
cpu_to_le32(rdma_wr(wr)->rkey);
417415
rc_sq_wqe->va =
418416
cpu_to_le64(rdma_wr(wr)->remote_addr);
419417
break;
420418
case IB_WR_RDMA_WRITE:
421-
roce_set_field(rc_sq_wqe->byte_4,
422-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
423-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
424-
HNS_ROCE_V2_WQE_OP_RDMA_WRITE);
419+
hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE;
425420
rc_sq_wqe->rkey =
426421
cpu_to_le32(rdma_wr(wr)->rkey);
427422
rc_sq_wqe->va =
428423
cpu_to_le64(rdma_wr(wr)->remote_addr);
429424
break;
430425
case IB_WR_RDMA_WRITE_WITH_IMM:
431-
roce_set_field(rc_sq_wqe->byte_4,
432-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
433-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
434-
HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM);
426+
hr_op = HNS_ROCE_V2_WQE_OP_RDMA_WRITE_WITH_IMM;
435427
rc_sq_wqe->rkey =
436428
cpu_to_le32(rdma_wr(wr)->rkey);
437429
rc_sq_wqe->va =
438430
cpu_to_le64(rdma_wr(wr)->remote_addr);
439431
break;
440432
case IB_WR_SEND:
441-
roce_set_field(rc_sq_wqe->byte_4,
442-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
443-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
444-
HNS_ROCE_V2_WQE_OP_SEND);
433+
hr_op = HNS_ROCE_V2_WQE_OP_SEND;
445434
break;
446435
case IB_WR_SEND_WITH_INV:
447-
roce_set_field(rc_sq_wqe->byte_4,
448-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
449-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
450-
HNS_ROCE_V2_WQE_OP_SEND_WITH_INV);
436+
hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_INV;
451437
break;
452438
case IB_WR_SEND_WITH_IMM:
453-
roce_set_field(rc_sq_wqe->byte_4,
454-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
455-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
456-
HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM);
439+
hr_op = HNS_ROCE_V2_WQE_OP_SEND_WITH_IMM;
457440
break;
458441
case IB_WR_LOCAL_INV:
459-
roce_set_field(rc_sq_wqe->byte_4,
460-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
461-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
462-
HNS_ROCE_V2_WQE_OP_LOCAL_INV);
442+
hr_op = HNS_ROCE_V2_WQE_OP_LOCAL_INV;
463443
break;
464444
case IB_WR_ATOMIC_CMP_AND_SWP:
465-
roce_set_field(rc_sq_wqe->byte_4,
466-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
467-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
468-
HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP);
445+
hr_op = HNS_ROCE_V2_WQE_OP_ATOM_CMP_AND_SWAP;
469446
break;
470447
case IB_WR_ATOMIC_FETCH_AND_ADD:
471-
roce_set_field(rc_sq_wqe->byte_4,
472-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
473-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
474-
HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD);
448+
hr_op = HNS_ROCE_V2_WQE_OP_ATOM_FETCH_AND_ADD;
475449
break;
476450
case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
477-
roce_set_field(rc_sq_wqe->byte_4,
478-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
479-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
480-
HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP);
451+
hr_op =
452+
HNS_ROCE_V2_WQE_OP_ATOM_MSK_CMP_AND_SWAP;
481453
break;
482454
case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
483-
roce_set_field(rc_sq_wqe->byte_4,
484-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
485-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
486-
HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD);
455+
hr_op =
456+
HNS_ROCE_V2_WQE_OP_ATOM_MSK_FETCH_AND_ADD;
487457
break;
488458
default:
489-
roce_set_field(rc_sq_wqe->byte_4,
490-
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
491-
V2_RC_SEND_WQE_BYTE_4_OPCODE_S,
492-
HNS_ROCE_V2_WQE_OP_MASK);
459+
hr_op = HNS_ROCE_V2_WQE_OP_MASK;
493460
break;
494461
}
495462

463+
roce_set_field(rc_sq_wqe->byte_4,
464+
V2_RC_SEND_WQE_BYTE_4_OPCODE_M,
465+
V2_RC_SEND_WQE_BYTE_4_OPCODE_S, hr_op);
496466
wqe += sizeof(struct hns_roce_v2_rc_send_wqe);
497467

498468
ret = set_rwqe_data_seg(ibqp, wr, rc_sq_wqe, wqe,

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