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Ingo Molnar
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Merge branch 'linus' into x86/urgent, to pick up dependencies for a fix
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2 parents 743146d + 710d60c commit ba4e06d

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‎Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
Alpine MSIX controller
2+
3+
See arm,gic-v3.txt for SPI and MSI definitions.
4+
5+
Required properties:
6+
7+
- compatible: should be "al,alpine-msix"
8+
- reg: physical base address and size of the registers
9+
- interrupt-parent: specifies the parent interrupt controller.
10+
- interrupt-controller: identifies the node as an interrupt controller
11+
- msi-controller: identifies the node as an PCI Message Signaled Interrupt
12+
controller
13+
- al,msi-base-spi: SPI base of the MSI frame
14+
- al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
15+
16+
Example:
17+
18+
msix: msix {
19+
compatible = "al,alpine-msix";
20+
reg = <0x0 0xfbe00000 0x0 0x100000>;
21+
interrupt-parent = <&gic>;
22+
interrupt-controller;
23+
msi-controller;
24+
al,msi-base-spi = <160>;
25+
al,msi-num-spis = <160>;
26+
};

‎Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ Main node required properties:
1616
"arm,cortex-a15-gic"
1717
"arm,cortex-a7-gic"
1818
"arm,cortex-a9-gic"
19+
"arm,eb11mp-gic"
1920
"arm,gic-400"
2021
"arm,pl390"
2122
"arm,tc11mp-gic"

‎Documentation/devicetree/bindings/interrupt-controller/marvell,odmi-controller.txt

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@@ -0,0 +1,44 @@
1+
2+
* Marvell ODMI for MSI support
3+
4+
Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5+
which can be used by on-board peripheral for MSI interrupts.
6+
7+
Required properties:
8+
9+
- compatible : The value here should contain:
10+
11+
"marvell,ap806-odmi-controller", "marvell,odmi-controller".
12+
13+
- interrupt,controller : Identifies the node as an interrupt controller.
14+
15+
- msi-controller : Identifies the node as an MSI controller.
16+
17+
- marvell,odmi-frames : Number of ODMI frames available. Each frame
18+
provides a number of events.
19+
20+
- reg : List of register definitions, one for each
21+
ODMI frame.
22+
23+
- marvell,spi-base : List of GIC base SPI interrupts, one for each
24+
ODMI frame. Those SPI interrupts are 0-based,
25+
i.e marvell,spi-base = <128> will use SPI #96.
26+
See Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
27+
for details about the GIC Device Tree binding.
28+
29+
- interrupt-parent : Reference to the parent interrupt controller.
30+
31+
Example:
32+
33+
odmi: odmi@300000 {
34+
compatible = "marvell,ap806-odm-controller",
35+
"marvell,odmi-controller";
36+
interrupt-controller;
37+
msi-controller;
38+
marvell,odmi-frames = <4>;
39+
reg = <0x300000 0x4000>,
40+
<0x304000 0x4000>,
41+
<0x308000 0x4000>,
42+
<0x30C000 0x4000>;
43+
marvell,spi-base = <128>, <136>, <144>, <152>;
44+
};

‎Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,12 @@ Optional properties:
2323
- mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
2424
to which the GIC may not route interrupts. Valid values are 2 - 7.
2525
This property is ignored if the CPU is started in EIC mode.
26+
- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
27+
reserved for IPIs.
28+
It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
29+
of the reserved range.
30+
If not specified, the driver will allocate the last 2 * number of VPEs in the
31+
system.
2632

2733
Required properties for timer sub-node:
2834
- compatible : Should be "mti,gic-timer".
@@ -44,6 +50,7 @@ Example:
4450
#interrupt-cells = <3>;
4551

4652
mti,reserved-cpu-vectors = <7>;
53+
mti,reserved-ipi-vectors = <40 8>;
4754

4855
timer {
4956
compatible = "mti,gic-timer";

‎Documentation/devicetree/bindings/interrupt-controller/sigma,smp8642-intc.txt

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@@ -0,0 +1,49 @@
1+
Sigma Designs SMP86xx/SMP87xx secondary interrupt controller
2+
3+
Required properties:
4+
- compatible: should be "sigma,smp8642-intc"
5+
- reg: physical address of MMIO region
6+
- ranges: address space mapping of child nodes
7+
- interrupt-parent: phandle of parent interrupt controller
8+
- interrupt-controller: boolean
9+
- #address-cells: should be <1>
10+
- #size-cells: should be <1>
11+
12+
One child node per control block with properties:
13+
- reg: address of registers for this control block
14+
- interrupt-controller: boolean
15+
- #interrupt-cells: should be <2>, interrupt index and flags per interrupts.txt
16+
- interrupts: interrupt spec of primary interrupt controller
17+
18+
Example:
19+
20+
interrupt-controller@6e000 {
21+
compatible = "sigma,smp8642-intc";
22+
reg = <0x6e000 0x400>;
23+
ranges = <0x0 0x6e000 0x400>;
24+
interrupt-parent = <&gic>;
25+
interrupt-controller;
26+
#address-cells = <1>;
27+
#size-cells = <1>;
28+
29+
irq0: interrupt-controller@0 {
30+
reg = <0x000 0x100>;
31+
interrupt-controller;
32+
#interrupt-cells = <2>;
33+
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
34+
};
35+
36+
irq1: interrupt-controller@100 {
37+
reg = <0x100 0x100>;
38+
interrupt-controller;
39+
#interrupt-cells = <2>;
40+
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
41+
};
42+
43+
irq2: interrupt-controller@300 {
44+
reg = <0x300 0x100>;
45+
interrupt-controller;
46+
#interrupt-cells = <2>;
47+
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
48+
};
49+
};

‎Documentation/kernel-parameters.txt

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Original file line numberDiff line numberDiff line change
@@ -666,7 +666,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
666666

667667
clearcpuid=BITNUM [X86]
668668
Disable CPUID feature X for the kernel. See
669-
arch/x86/include/asm/cpufeature.h for the valid bit
669+
arch/x86/include/asm/cpufeatures.h for the valid bit
670670
numbers. Note the Linux specific bits are not necessarily
671671
stable over kernel options, but the vendor specific
672672
ones should be.
@@ -1687,6 +1687,15 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
16871687
ip= [IP_PNP]
16881688
See Documentation/filesystems/nfs/nfsroot.txt.
16891689

1690+
irqaffinity= [SMP] Set the default irq affinity mask
1691+
Format:
1692+
<cpu number>,...,<cpu number>
1693+
or
1694+
<cpu number>-<cpu number>
1695+
(must be a positive range in ascending order)
1696+
or a mixture
1697+
<cpu number>,...,<cpu number>-<cpu number>
1698+
16901699
irqfixup [HW]
16911700
When an interrupt is not handled search all handlers
16921701
for it. Intended to get systems with badly broken
@@ -2566,6 +2575,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
25662575

25672576
nointroute [IA-64]
25682577

2578+
noinvpcid [X86] Disable the INVPCID cpu feature.
2579+
25692580
nojitter [IA-64] Disables jitter checking for ITC timers.
25702581

25712582
no-kvmclock [X86,KVM] Disable paravirtualized KVM clock driver

‎Documentation/ptp/testptp.c

Lines changed: 4 additions & 2 deletions
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@@ -277,13 +277,15 @@ int main(int argc, char *argv[])
277277
" %d external time stamp channels\n"
278278
" %d programmable periodic signals\n"
279279
" %d pulse per second\n"
280-
" %d programmable pins\n",
280+
" %d programmable pins\n"
281+
" %d cross timestamping\n",
281282
caps.max_adj,
282283
caps.n_alarm,
283284
caps.n_ext_ts,
284285
caps.n_per_out,
285286
caps.pps,
286-
caps.n_pins);
287+
caps.n_pins,
288+
caps.cross_timestamping);
287289
}
288290
}
289291

‎Documentation/x86/early-microcode.txt

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@@ -40,3 +40,28 @@ cp ../microcode.bin kernel/x86/microcode/GenuineIntel.bin (or AuthenticAMD.bin)
4040
find . | cpio -o -H newc >../ucode.cpio
4141
cd ..
4242
cat ucode.cpio /boot/initrd-3.5.0.img >/boot/initrd-3.5.0.ucode.img
43+
44+
Builtin microcode
45+
=================
46+
47+
We can also load builtin microcode supplied through the regular firmware
48+
builtin method CONFIG_FIRMWARE_IN_KERNEL. Here's an example:
49+
50+
CONFIG_FIRMWARE_IN_KERNEL=y
51+
CONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin"
52+
CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware"
53+
54+
This basically means, you have the following tree structure locally:
55+
56+
/lib/firmware/
57+
|-- amd-ucode
58+
...
59+
| |-- microcode_amd_fam15h.bin
60+
...
61+
|-- intel-ucode
62+
...
63+
| |-- 06-3a-09
64+
...
65+
66+
so that the build system can find those files and integrate them into
67+
the final kernel image. The early loader finds them and applies them.

‎Documentation/x86/x86_64/boot-options.txt

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@@ -60,6 +60,8 @@ Machine check
6060
threshold to 1. Enabling this may make memory predictive failure
6161
analysis less effective if the bios sets thresholds for memory
6262
errors since we will not see details for all errors.
63+
mce=recovery
64+
Force-enable recoverable machine check code paths
6365

6466
nomce (for compatibility with i386): same as mce=off
6567

‎MAINTAINERS

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2422,6 +2422,7 @@ F: arch/mips/bmips/*
24222422
F: arch/mips/include/asm/mach-bmips/*
24232423
F: arch/mips/kernel/*bmips*
24242424
F: arch/mips/boot/dts/brcm/bcm*.dts*
2425+
F: drivers/irqchip/irq-bcm63*
24252426
F: drivers/irqchip/irq-bcm7*
24262427
F: drivers/irqchip/irq-brcmstb*
24272428
F: include/linux/bcm963xx_nvram.h

‎arch/alpha/kernel/smp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ smp_callin(void)
168168
cpuid, current, current->active_mm));
169169

170170
preempt_disable();
171-
cpu_startup_entry(CPUHP_ONLINE);
171+
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
172172
}
173173

174174
/* Wait until hwrpb->txrdy is clear for cpu. Return -1 on timeout. */

‎arch/arc/kernel/smp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -142,7 +142,7 @@ void start_kernel_secondary(void)
142142

143143
local_irq_enable();
144144
preempt_disable();
145-
cpu_startup_entry(CPUHP_ONLINE);
145+
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
146146
}
147147

148148
/*

‎arch/arm/kernel/smp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -409,7 +409,7 @@ asmlinkage void secondary_start_kernel(void)
409409
/*
410410
* OK, it's off to the idle thread for us
411411
*/
412-
cpu_startup_entry(CPUHP_ONLINE);
412+
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
413413
}
414414

415415
void __init smp_cpus_done(unsigned int max_cpus)

‎arch/arm/mach-mvebu/Kconfig

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,6 @@ menuconfig ARCH_MVEBU
33
depends on ARCH_MULTI_V7 || ARCH_MULTI_V5
44
select ARCH_SUPPORTS_BIG_ENDIAN
55
select CLKSRC_MMIO
6-
select GENERIC_IRQ_CHIP
76
select PINCTRL
87
select PLAT_ORION
98
select SOC_BUS
@@ -29,6 +28,7 @@ config MACH_ARMADA_370
2928
bool "Marvell Armada 370 boards"
3029
depends on ARCH_MULTI_V7
3130
select ARMADA_370_CLK
31+
select ARMADA_370_XP_IRQ
3232
select CPU_PJ4B
3333
select MACH_MVEBU_V7
3434
select PINCTRL_ARMADA_370
@@ -39,6 +39,7 @@ config MACH_ARMADA_370
3939
config MACH_ARMADA_375
4040
bool "Marvell Armada 375 boards"
4141
depends on ARCH_MULTI_V7
42+
select ARMADA_370_XP_IRQ
4243
select ARM_ERRATA_720789
4344
select ARM_ERRATA_753970
4445
select ARM_GIC
@@ -58,6 +59,7 @@ config MACH_ARMADA_38X
5859
select ARM_ERRATA_720789
5960
select ARM_ERRATA_753970
6061
select ARM_GIC
62+
select ARMADA_370_XP_IRQ
6163
select ARMADA_38X_CLK
6264
select HAVE_ARM_SCU
6365
select HAVE_ARM_TWD if SMP
@@ -72,6 +74,7 @@ config MACH_ARMADA_39X
7274
bool "Marvell Armada 39x boards"
7375
depends on ARCH_MULTI_V7
7476
select ARM_GIC
77+
select ARMADA_370_XP_IRQ
7578
select ARMADA_39X_CLK
7679
select CACHE_L2X0
7780
select HAVE_ARM_SCU
@@ -86,6 +89,7 @@ config MACH_ARMADA_39X
8689
config MACH_ARMADA_XP
8790
bool "Marvell Armada XP boards"
8891
depends on ARCH_MULTI_V7
92+
select ARMADA_370_XP_IRQ
8993
select ARMADA_XP_CLK
9094
select CPU_PJ4B
9195
select MACH_MVEBU_V7

‎arch/arm64/kernel/smp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,7 @@ asmlinkage void secondary_start_kernel(void)
195195
/*
196196
* OK, it's off to the idle thread for us
197197
*/
198-
cpu_startup_entry(CPUHP_ONLINE);
198+
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
199199
}
200200

201201
#ifdef CONFIG_HOTPLUG_CPU

‎arch/blackfin/mach-common/smp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -333,7 +333,7 @@ void secondary_start_kernel(void)
333333

334334
/* We are done with local CPU inits, unblock the boot CPU. */
335335
set_cpu_online(cpu, true);
336-
cpu_startup_entry(CPUHP_ONLINE);
336+
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
337337
}
338338

339339
void __init smp_prepare_boot_cpu(void)

‎arch/hexagon/kernel/smp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,7 @@ void start_secondary(void)
180180

181181
local_irq_enable();
182182

183-
cpu_startup_entry(CPUHP_ONLINE);
183+
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
184184
}
185185

186186

‎arch/ia64/kernel/smpboot.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -454,7 +454,7 @@ start_secondary (void *unused)
454454
preempt_disable();
455455
smp_callin();
456456

457-
cpu_startup_entry(CPUHP_ONLINE);
457+
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
458458
return 0;
459459
}
460460

‎arch/m32r/kernel/smpboot.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -432,7 +432,7 @@ int __init start_secondary(void *unused)
432432
*/
433433
local_flush_tlb_all();
434434

435-
cpu_startup_entry(CPUHP_ONLINE);
435+
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
436436
return 0;
437437
}
438438

‎arch/metag/kernel/smp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -396,7 +396,7 @@ asmlinkage void secondary_start_kernel(void)
396396
/*
397397
* OK, it's off to the idle thread for us
398398
*/
399-
cpu_startup_entry(CPUHP_ONLINE);
399+
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
400400
}
401401

402402
void __init smp_cpus_done(unsigned int max_cpus)

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