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ashok-rajIngo Molnar
ashok-raj
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Ingo Molnar
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x86/mce: Add Local MCE definitions
Add required definitions to support Local Machine Check Exceptions. Historically, machine check exceptions on Intel x86 processors have been broadcast to all logical processors in the system. Upcoming CPUs will support an opt-in mechanism to request some machine check exceptions be delivered to a single logical processor experiencing the fault. See http://www.intel.com/sdm Volume 3, System Programming Guide, chapter 15 for more information on MSRs and documentation on Local MCE. Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1433436928-31903-15-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar <mingo@kernel.org>
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‎arch/x86/include/asm/mce.h

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@@ -17,11 +17,16 @@
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#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
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#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
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#define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */
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#define MCG_LMCE_P (1ULL<<27) /* Local machine check supported */
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/* MCG_STATUS register defines */
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#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
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#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
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#define MCG_STATUS_LMCES (1ULL<<3) /* LMCE signaled */
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/* MCG_EXT_CTL register defines */
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#define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
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/* MCi_STATUS register defines */
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#define MCI_STATUS_VAL (1ULL<<63) /* valid error */

‎arch/x86/include/uapi/asm/msr-index.h

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#define MSR_IA32_MCG_CAP 0x00000179
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#define MSR_IA32_MCG_STATUS 0x0000017a
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#define MSR_IA32_MCG_CTL 0x0000017b
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#define MSR_IA32_MCG_EXT_CTL 0x000004d0
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#define MSR_OFFCORE_RSP_0 0x000001a6
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#define MSR_OFFCORE_RSP_1 0x000001a7
@@ -379,6 +380,7 @@
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#define FEATURE_CONTROL_LOCKED (1<<0)
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#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
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#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
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#define FEATURE_CONTROL_LMCE (1<<20)
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#define MSR_IA32_APICBASE 0x0000001b
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#define MSR_IA32_APICBASE_BSP (1<<8)

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