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amirvdavem330
amirv
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davem330
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net/mlx4_en: num cores tx rings for every UP
Change the TX ring scheme such that the number of rings for untagged packets and for tagged packets (per each of the vlan priorities) is the same, unlike the current situation where for tagged traffic there's one ring per priority and for untagged rings as the number of core. Queue selection is done as follows: If the mqprio qdisc is operates on the interface, such that the core networking code invoked the device setup_tc ndo callback, a mapping of skb->priority => queue set is forced - for both, tagged and untagged traffic. Else, the egress map skb->priority => User priority is used for tagged traffic, and all untagged traffic is sent through tx rings of UP 0. The patch follows the convergence of discussing that issue with John Fastabend over this thread http://comments.gmane.org/gmane.linux.network/229877 Cc: John Fastabend <john.r.fastabend@intel.com> Cc: Liran Liss <liranl@mellanox.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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+47
-24
lines changed

4 files changed

+47
-24
lines changed

‎drivers/net/ethernet/mellanox/mlx4/en_main.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,8 @@ static int mlx4_en_get_profile(struct mlx4_en_dev *mdev)
101101
int i;
102102

103103
params->udp_rss = udp_rss;
104+
params->num_tx_rings_p_up = min_t(int, num_online_cpus(),
105+
MLX4_EN_MAX_TX_RING_P_UP);
104106
if (params->udp_rss && !(mdev->dev->caps.flags
105107
& MLX4_DEV_CAP_FLAG_UDP_RSS)) {
106108
mlx4_warn(mdev, "UDP RSS is not supported on this device.\n");
@@ -113,8 +115,8 @@ static int mlx4_en_get_profile(struct mlx4_en_dev *mdev)
113115
params->prof[i].tx_ppp = pfctx;
114116
params->prof[i].tx_ring_size = MLX4_EN_DEF_TX_RING_SIZE;
115117
params->prof[i].rx_ring_size = MLX4_EN_DEF_RX_RING_SIZE;
116-
params->prof[i].tx_ring_num = MLX4_EN_NUM_TX_RINGS +
117-
MLX4_EN_NUM_PPP_RINGS;
118+
params->prof[i].tx_ring_num = params->num_tx_rings_p_up *
119+
MLX4_EN_NUM_UP;
118120
params->prof[i].rss_rings = 0;
119121
}
120122

‎drivers/net/ethernet/mellanox/mlx4/en_netdev.c

Lines changed: 30 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,22 @@
4747

4848
static int mlx4_en_setup_tc(struct net_device *dev, u8 up)
4949
{
50-
if (up != MLX4_EN_NUM_UP)
50+
struct mlx4_en_priv *priv = netdev_priv(dev);
51+
int i;
52+
unsigned int q, offset = 0;
53+
54+
if (up && up != MLX4_EN_NUM_UP)
5155
return -EINVAL;
5256

57+
netdev_set_num_tc(dev, up);
58+
59+
/* Partition Tx queues evenly amongst UP's */
60+
q = priv->tx_ring_num / up;
61+
for (i = 0; i < up; i++) {
62+
netdev_set_tc_queue(dev, i, q, offset);
63+
offset += q;
64+
}
65+
5366
return 0;
5467
}
5568

@@ -661,7 +674,7 @@ int mlx4_en_start_port(struct net_device *dev)
661674
/* Configure ring */
662675
tx_ring = &priv->tx_ring[i];
663676
err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
664-
max(0, i - MLX4_EN_NUM_TX_RINGS));
677+
i / priv->mdev->profile.num_tx_rings_p_up);
665678
if (err) {
666679
en_err(priv, "Failed allocating Tx ring\n");
667680
mlx4_en_deactivate_cq(priv, cq);
@@ -986,6 +999,9 @@ void mlx4_en_destroy_netdev(struct net_device *dev)
986999

9871000
mlx4_en_free_resources(priv);
9881001

1002+
kfree(priv->tx_ring);
1003+
kfree(priv->tx_cq);
1004+
9891005
free_netdev(dev);
9901006
}
9911007

@@ -1091,6 +1107,18 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
10911107
priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
10921108
MLX4_WQE_CTRL_SOLICITED);
10931109
priv->tx_ring_num = prof->tx_ring_num;
1110+
priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring) *
1111+
priv->tx_ring_num, GFP_KERNEL);
1112+
if (!priv->tx_ring) {
1113+
err = -ENOMEM;
1114+
goto out;
1115+
}
1116+
priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq) * priv->tx_ring_num,
1117+
GFP_KERNEL);
1118+
if (!priv->tx_cq) {
1119+
err = -ENOMEM;
1120+
goto out;
1121+
}
10941122
priv->rx_ring_num = prof->rx_ring_num;
10951123
priv->mac_index = -1;
10961124
priv->msg_enable = MLX4_EN_MSG_LEVEL;
@@ -1138,15 +1166,6 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
11381166
netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
11391167
netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
11401168

1141-
netdev_set_num_tc(dev, MLX4_EN_NUM_UP);
1142-
1143-
/* First 9 rings are for UP 0 */
1144-
netdev_set_tc_queue(dev, 0, MLX4_EN_NUM_TX_RINGS + 1, 0);
1145-
1146-
/* Partition Tx queues evenly amongst UP's 1-7 */
1147-
for (i = 1; i < MLX4_EN_NUM_UP; i++)
1148-
netdev_set_tc_queue(dev, i, 1, MLX4_EN_NUM_TX_RINGS + i);
1149-
11501169
SET_ETHTOOL_OPS(dev, &mlx4_en_ethtool_ops);
11511170

11521171
/* Set defualt MAC */

‎drivers/net/ethernet/mellanox/mlx4/en_tx.c

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -525,14 +525,17 @@ static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *sk
525525

526526
u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb)
527527
{
528-
u16 vlan_tag = 0;
528+
struct mlx4_en_priv *priv = netdev_priv(dev);
529+
u16 rings_p_up = priv->mdev->profile.num_tx_rings_p_up;
530+
u8 up = 0;
529531

530-
if (vlan_tx_tag_present(skb)) {
531-
vlan_tag = vlan_tx_tag_get(skb);
532-
return MLX4_EN_NUM_TX_RINGS + (vlan_tag >> 13);
533-
}
532+
if (dev->num_tc)
533+
return skb_tx_hash(dev, skb);
534+
535+
if (vlan_tx_tag_present(skb))
536+
up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT;
534537

535-
return skb_tx_hash(dev, skb);
538+
return __skb_tx_hash(dev, skb, rings_p_up) + up * rings_p_up;
536539
}
537540

538541
static void mlx4_bf_copy(void __iomem *dst, unsigned long *src, unsigned bytecnt)

‎drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -111,9 +111,7 @@ enum {
111111
#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
112112

113113
#define MLX4_EN_SMALL_PKT_SIZE 64
114-
#define MLX4_EN_NUM_TX_RINGS 8
115-
#define MLX4_EN_NUM_PPP_RINGS 8
116-
#define MAX_TX_RINGS (MLX4_EN_NUM_TX_RINGS + MLX4_EN_NUM_PPP_RINGS)
114+
#define MLX4_EN_MAX_TX_RING_P_UP 32
117115
#define MLX4_EN_NUM_UP 8
118116
#define MLX4_EN_DEF_TX_RING_SIZE 512
119117
#define MLX4_EN_DEF_RX_RING_SIZE 1024
@@ -339,6 +337,7 @@ struct mlx4_en_profile {
339337
u32 active_ports;
340338
u32 small_pkt_int;
341339
u8 no_reset;
340+
u8 num_tx_rings_p_up;
342341
struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
343342
};
344343

@@ -477,9 +476,9 @@ struct mlx4_en_priv {
477476
u16 num_frags;
478477
u16 log_rx_info;
479478

480-
struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
479+
struct mlx4_en_tx_ring *tx_ring;
481480
struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
482-
struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
481+
struct mlx4_en_cq *tx_cq;
483482
struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
484483
struct work_struct mcast_task;
485484
struct work_struct mac_task;

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