@@ -2337,6 +2337,32 @@ static int i9xx_format_to_fourcc(int format)
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}
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}
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+ static int skl_format_to_fourcc (int format , bool rgb_order , bool alpha )
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+ {
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+ switch (format ) {
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+ case PLANE_CTL_FORMAT_RGB_565 :
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+ return DRM_FORMAT_RGB565 ;
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+ default :
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+ case PLANE_CTL_FORMAT_XRGB_8888 :
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+ if (rgb_order ) {
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+ if (alpha )
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+ return DRM_FORMAT_ABGR8888 ;
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+ else
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+ return DRM_FORMAT_XBGR8888 ;
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+ } else {
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+ if (alpha )
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+ return DRM_FORMAT_ARGB8888 ;
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+ else
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+ return DRM_FORMAT_XRGB8888 ;
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+ }
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+ case PLANE_CTL_FORMAT_XRGB_2101010 :
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+ if (rgb_order )
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+ return DRM_FORMAT_XBGR2101010 ;
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+ else
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+ return DRM_FORMAT_XRGB2101010 ;
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+ }
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+ }
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+
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static bool intel_alloc_plane_obj (struct intel_crtc * crtc ,
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struct intel_plane_config * plane_config )
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{
@@ -7573,6 +7599,74 @@ static void skylake_get_pfit_config(struct intel_crtc *crtc,
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}
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}
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+ static void skylake_get_plane_config (struct intel_crtc * crtc ,
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+ struct intel_plane_config * plane_config )
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+ {
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+ struct drm_device * dev = crtc -> base .dev ;
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+ struct drm_i915_private * dev_priv = dev -> dev_private ;
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+ u32 val , base , offset , stride_mult ;
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+ int pipe = crtc -> pipe ;
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+ int fourcc , pixel_format ;
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+ int aligned_height ;
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+ struct drm_framebuffer * fb ;
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+
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+ fb = kzalloc (sizeof (struct intel_framebuffer ), GFP_KERNEL );
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+ if (!fb ) {
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+ DRM_DEBUG_KMS ("failed to alloc fb\n" );
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+ return ;
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+ }
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+
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+ val = I915_READ (PLANE_CTL (pipe , 0 ));
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+ if (val & PLANE_CTL_TILED_MASK )
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+ plane_config -> tiling = I915_TILING_X ;
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+
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+ pixel_format = val & PLANE_CTL_FORMAT_MASK ;
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+ fourcc = skl_format_to_fourcc (pixel_format ,
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+ val & PLANE_CTL_ORDER_RGBX ,
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+ val & PLANE_CTL_ALPHA_MASK );
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+ fb -> pixel_format = fourcc ;
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+ fb -> bits_per_pixel = drm_format_plane_cpp (fourcc , 0 ) * 8 ;
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+
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+ base = I915_READ (PLANE_SURF (pipe , 0 )) & 0xfffff000 ;
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+ plane_config -> base = base ;
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+
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+ offset = I915_READ (PLANE_OFFSET (pipe , 0 ));
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+
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+ val = I915_READ (PLANE_SIZE (pipe , 0 ));
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+ fb -> height = ((val >> 16 ) & 0xfff ) + 1 ;
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+ fb -> width = ((val >> 0 ) & 0x1fff ) + 1 ;
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+
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+ val = I915_READ (PLANE_STRIDE (pipe , 0 ));
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+ switch (plane_config -> tiling ) {
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+ case I915_TILING_NONE :
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+ stride_mult = 64 ;
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+ break ;
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+ case I915_TILING_X :
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+ stride_mult = 512 ;
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+ break ;
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+ default :
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+ MISSING_CASE (plane_config -> tiling );
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+ goto error ;
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+ }
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+ fb -> pitches [0 ] = (val & 0x3ff ) * stride_mult ;
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+
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+ aligned_height = intel_fb_align_height (dev , fb -> height ,
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+ plane_config -> tiling );
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+
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+ plane_config -> size = ALIGN (fb -> pitches [0 ] * aligned_height , PAGE_SIZE );
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+
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+ DRM_DEBUG_KMS ("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" ,
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+ pipe_name (pipe ), fb -> width , fb -> height ,
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+ fb -> bits_per_pixel , base , fb -> pitches [0 ],
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+ plane_config -> size );
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+
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+ crtc -> base .primary -> fb = fb ;
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+ return ;
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+
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+ error :
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+ kfree (fb );
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+ }
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+
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static void ironlake_get_pfit_config (struct intel_crtc * crtc ,
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struct intel_crtc_state * pipe_config )
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{
@@ -12668,20 +12762,26 @@ static void intel_init_display(struct drm_device *dev)
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else
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dev_priv -> display .find_dpll = i9xx_find_best_dpll ;
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- if (HAS_DDI (dev )) {
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+ if (INTEL_INFO (dev )-> gen >= 9 ) {
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+ dev_priv -> display .get_pipe_config = haswell_get_pipe_config ;
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+ dev_priv -> display .get_plane_config = skylake_get_plane_config ;
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+ dev_priv -> display .crtc_compute_clock =
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+ haswell_crtc_compute_clock ;
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+ dev_priv -> display .crtc_enable = haswell_crtc_enable ;
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+ dev_priv -> display .crtc_disable = haswell_crtc_disable ;
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+ dev_priv -> display .off = ironlake_crtc_off ;
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+ dev_priv -> display .update_primary_plane =
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+ skylake_update_primary_plane ;
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+ } else if (HAS_DDI (dev )) {
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dev_priv -> display .get_pipe_config = haswell_get_pipe_config ;
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dev_priv -> display .get_plane_config = ironlake_get_plane_config ;
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dev_priv -> display .crtc_compute_clock =
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haswell_crtc_compute_clock ;
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dev_priv -> display .crtc_enable = haswell_crtc_enable ;
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dev_priv -> display .crtc_disable = haswell_crtc_disable ;
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dev_priv -> display .off = ironlake_crtc_off ;
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- if (INTEL_INFO (dev )-> gen >= 9 )
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- dev_priv -> display .update_primary_plane =
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- skylake_update_primary_plane ;
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- else
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- dev_priv -> display .update_primary_plane =
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- ironlake_update_primary_plane ;
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+ dev_priv -> display .update_primary_plane =
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+ ironlake_update_primary_plane ;
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} else if (HAS_PCH_SPLIT (dev )) {
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dev_priv -> display .get_pipe_config = ironlake_get_pipe_config ;
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dev_priv -> display .get_plane_config = ironlake_get_plane_config ;
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