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chelsiocudbgdavem330
chelsiocudbg
authored and
davem330
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cxgb4: collect TX rate limit info in UP CIM logs
Collect TX rate limiting related information in UP CIM logs. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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+100
-39
lines changed

5 files changed

+100
-39
lines changed

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h

Lines changed: 49 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -405,37 +405,55 @@ static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
405405
{0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
406406
};
407407

408-
static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM] = {
409-
{0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
410-
{0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */
411-
{0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
412-
{0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
413-
{0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
414-
{0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
415-
{0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
416-
{0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
417-
{0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
418-
{0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
419-
{0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
420-
{0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
421-
{0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
422-
423-
};
424-
425-
static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM] = {
426-
{0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
427-
{0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */
428-
{0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
429-
{0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
430-
{0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
431-
{0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
432-
{0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
433-
{0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
434-
{0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
435-
{0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
436-
{0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
437-
{0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
438-
{0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
408+
static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
409+
{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
410+
{0x7b50, 0x7b54, 0x2080, 0x1d, 0}, /* up_cim_2080_to_20fc */
411+
{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
412+
{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
413+
{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
414+
{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
415+
{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
416+
{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
417+
{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
418+
{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
419+
{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
420+
{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
421+
{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
422+
{0x7b50, 0x7b54, 0x2900, 0x4, 0x4}, /* up_cim_2900_to_3d40 */
423+
{0x7b50, 0x7b54, 0x2904, 0x4, 0x4}, /* up_cim_2904_to_3d44 */
424+
{0x7b50, 0x7b54, 0x2908, 0x4, 0x4}, /* up_cim_2908_to_3d48 */
425+
{0x7b50, 0x7b54, 0x2910, 0x4, 0x4}, /* up_cim_2910_to_3d4c */
426+
{0x7b50, 0x7b54, 0x2914, 0x4, 0x4}, /* up_cim_2914_to_3d50 */
427+
{0x7b50, 0x7b54, 0x2920, 0x10, 0x10}, /* up_cim_2920_to_2a10 */
428+
{0x7b50, 0x7b54, 0x2924, 0x10, 0x10}, /* up_cim_2924_to_2a14 */
429+
{0x7b50, 0x7b54, 0x2928, 0x10, 0x10}, /* up_cim_2928_to_2a18 */
430+
{0x7b50, 0x7b54, 0x292c, 0x10, 0x10}, /* up_cim_292c_to_2a1c */
431+
};
432+
433+
static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM + 1] = {
434+
{0x7b50, 0x7b54, 0x2000, 0x20, 0}, /* up_cim_2000_to_207c */
435+
{0x7b50, 0x7b54, 0x2080, 0x19, 0}, /* up_cim_2080_to_20ec */
436+
{0x7b50, 0x7b54, 0x00, 0x20, 0}, /* up_cim_00_to_7c */
437+
{0x7b50, 0x7b54, 0x80, 0x20, 0}, /* up_cim_80_to_fc */
438+
{0x7b50, 0x7b54, 0x100, 0x11, 0}, /* up_cim_100_to_14c */
439+
{0x7b50, 0x7b54, 0x200, 0x10, 0}, /* up_cim_200_to_23c */
440+
{0x7b50, 0x7b54, 0x240, 0x2, 0}, /* up_cim_240_to_244 */
441+
{0x7b50, 0x7b54, 0x250, 0x2, 0}, /* up_cim_250_to_254 */
442+
{0x7b50, 0x7b54, 0x260, 0x2, 0}, /* up_cim_260_to_264 */
443+
{0x7b50, 0x7b54, 0x270, 0x2, 0}, /* up_cim_270_to_274 */
444+
{0x7b50, 0x7b54, 0x280, 0x20, 0}, /* up_cim_280_to_2fc */
445+
{0x7b50, 0x7b54, 0x300, 0x20, 0}, /* up_cim_300_to_37c */
446+
{0x7b50, 0x7b54, 0x380, 0x14, 0}, /* up_cim_380_to_3cc */
447+
{0x7b50, 0x7b54, 0x2900, 0x4, 0x4}, /* up_cim_2900_to_3d40 */
448+
{0x7b50, 0x7b54, 0x2904, 0x4, 0x4}, /* up_cim_2904_to_3d44 */
449+
{0x7b50, 0x7b54, 0x2908, 0x4, 0x4}, /* up_cim_2908_to_3d48 */
450+
{0x7b50, 0x7b54, 0x2910, 0x4, 0x4}, /* up_cim_2910_to_3d4c */
451+
{0x7b50, 0x7b54, 0x2914, 0x4, 0x4}, /* up_cim_2914_to_3d50 */
452+
{0x7b50, 0x7b54, 0x2918, 0x4, 0x4}, /* up_cim_2918_to_3d54 */
453+
{0x7b50, 0x7b54, 0x291c, 0x4, 0x4}, /* up_cim_291c_to_3d58 */
454+
{0x7b50, 0x7b54, 0x2924, 0x10, 0x10}, /* up_cim_2924_to_2914 */
455+
{0x7b50, 0x7b54, 0x2928, 0x10, 0x10}, /* up_cim_2928_to_2a18 */
456+
{0x7b50, 0x7b54, 0x292c, 0x10, 0x10}, /* up_cim_292c_to_2a1c */
439457
};
440458

441459
static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
/* Error codes */
2222
#define CUDBG_STATUS_NO_MEM -19
2323
#define CUDBG_STATUS_ENTITY_NOT_FOUND -24
24+
#define CUDBG_STATUS_NOT_IMPLEMENTED -28
2425
#define CUDBG_SYSTEM_ERROR -29
2526
#define CUDBG_STATUS_CCLK_NOT_DEFINED -32
2627

‎drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c

Lines changed: 40 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2422,11 +2422,21 @@ int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
24222422
{
24232423
struct adapter *padap = pdbg_init->adap;
24242424
struct cudbg_buffer temp_buff = { 0 };
2425+
u32 local_offset, local_range;
24252426
struct ireg_buf *up_cim;
2427+
u32 size, j, iter;
2428+
u32 instance = 0;
24262429
int i, rc, n;
2427-
u32 size;
24282430

2429-
n = sizeof(t5_up_cim_reg_array) / (IREG_NUM_ELEM * sizeof(u32));
2431+
if (is_t5(padap->params.chip))
2432+
n = sizeof(t5_up_cim_reg_array) /
2433+
((IREG_NUM_ELEM + 1) * sizeof(u32));
2434+
else if (is_t6(padap->params.chip))
2435+
n = sizeof(t6_up_cim_reg_array) /
2436+
((IREG_NUM_ELEM + 1) * sizeof(u32));
2437+
else
2438+
return CUDBG_STATUS_NOT_IMPLEMENTED;
2439+
24302440
size = sizeof(struct ireg_buf) * n;
24312441
rc = cudbg_get_buff(dbg_buff, size, &temp_buff);
24322442
if (rc)
@@ -2444,20 +2454,43 @@ int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
24442454
t5_up_cim_reg_array[i][2];
24452455
up_cim_reg->ireg_offset_range =
24462456
t5_up_cim_reg_array[i][3];
2457+
instance = t5_up_cim_reg_array[i][4];
24472458
} else if (is_t6(padap->params.chip)) {
24482459
up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0];
24492460
up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1];
24502461
up_cim_reg->ireg_local_offset =
24512462
t6_up_cim_reg_array[i][2];
24522463
up_cim_reg->ireg_offset_range =
24532464
t6_up_cim_reg_array[i][3];
2465+
instance = t6_up_cim_reg_array[i][4];
24542466
}
24552467

2456-
rc = t4_cim_read(padap, up_cim_reg->ireg_local_offset,
2457-
up_cim_reg->ireg_offset_range, buff);
2458-
if (rc) {
2459-
cudbg_put_buff(&temp_buff, dbg_buff);
2460-
return rc;
2468+
switch (instance) {
2469+
case NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES:
2470+
iter = up_cim_reg->ireg_offset_range;
2471+
local_offset = 0x120;
2472+
local_range = 1;
2473+
break;
2474+
case NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES:
2475+
iter = up_cim_reg->ireg_offset_range;
2476+
local_offset = 0x10;
2477+
local_range = 1;
2478+
break;
2479+
default:
2480+
iter = 1;
2481+
local_offset = 0;
2482+
local_range = up_cim_reg->ireg_offset_range;
2483+
break;
2484+
}
2485+
2486+
for (j = 0; j < iter; j++, buff++) {
2487+
rc = t4_cim_read(padap,
2488+
up_cim_reg->ireg_local_offset +
2489+
(j * local_offset), local_range, buff);
2490+
if (rc) {
2491+
cudbg_put_buff(&temp_buff, dbg_buff);
2492+
return rc;
2493+
}
24612494
}
24622495
up_cim++;
24632496
}

‎drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -274,7 +274,13 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
274274
len = sizeof(struct cudbg_ulptx_la);
275275
break;
276276
case CUDBG_UP_CIM_INDIRECT:
277-
n = sizeof(t5_up_cim_reg_array) / (IREG_NUM_ELEM * sizeof(u32));
277+
n = 0;
278+
if (is_t5(adap->params.chip))
279+
n = sizeof(t5_up_cim_reg_array) /
280+
((IREG_NUM_ELEM + 1) * sizeof(u32));
281+
else if (is_t6(adap->params.chip))
282+
n = sizeof(t6_up_cim_reg_array) /
283+
((IREG_NUM_ELEM + 1) * sizeof(u32));
278284
len = sizeof(struct ireg_buf) * n;
279285
break;
280286
case CUDBG_PBT_TABLE:

‎drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,9 @@
4545
#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
4646
#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
4747

48+
#define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
49+
#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
50+
4851
#define MYPORT_BASE 0x1c000
4952
#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
5053

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