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Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux
Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
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‎Documentation/clk.txt

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ the operations defined in clk.h:
7474
long (*determine_rate)(struct clk_hw *hw,
7575
unsigned long rate,
7676
unsigned long *best_parent_rate,
77-
struct clk **best_parent_clk);
77+
struct clk_hw **best_parent_clk);
7878
int (*set_parent)(struct clk_hw *hw, u8 index);
7979
u8 (*get_parent)(struct clk_hw *hw);
8080
int (*set_rate)(struct clk_hw *hw,

‎Documentation/devicetree/bindings/clock/exynos4415-clock.txt

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
* Samsung Exynos4415 Clock Controller
2+
3+
The Exynos4415 clock controller generates and supplies clock to various
4+
consumer devices within the Exynos4415 SoC.
5+
6+
Required properties:
7+
8+
- compatible: should be one of the following:
9+
- "samsung,exynos4415-cmu" - for the main system clocks controller
10+
(CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
11+
- "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
12+
Controller (DMC) domain clock controller.
13+
14+
- reg: physical base address of the controller and length of memory mapped
15+
region.
16+
17+
- #clock-cells: should be 1.
18+
19+
Each clock is assigned an identifier and client nodes can use this identifier
20+
to specify the clock which they consume.
21+
22+
All available clocks are defined as preprocessor macros in
23+
dt-bindings/clock/exynos4415.h header and can be used in device
24+
tree sources.
25+
26+
Example 1: An example of a clock controller node is listed below.
27+
28+
cmu: clock-controller@10030000 {
29+
compatible = "samsung,exynos4415-cmu";
30+
reg = <0x10030000 0x18000>;
31+
#clock-cells = <1>;
32+
};
33+
34+
cmu-dmc: clock-controller@105C0000 {
35+
compatible = "samsung,exynos4415-cmu-dmc";
36+
reg = <0x105C0000 0x3000>;
37+
#clock-cells = <1>;
38+
};

‎Documentation/devicetree/bindings/clock/exynos7-clock.txt

Lines changed: 93 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,93 @@
1+
* Samsung Exynos7 Clock Controller
2+
3+
Exynos7 clock controller has various blocks which are instantiated
4+
independently from the device-tree. These clock controllers
5+
generate and supply clocks to various hardware blocks within
6+
the SoC.
7+
8+
Each clock is assigned an identifier and client nodes can use
9+
this identifier to specify the clock which they consume. All
10+
available clocks are defined as preprocessor macros in
11+
dt-bindings/clock/exynos7-clk.h header and can be used in
12+
device tree sources.
13+
14+
External clocks:
15+
16+
There are several clocks that are generated outside the SoC. It
17+
is expected that they are defined using standard clock bindings
18+
with following clock-output-names:
19+
20+
- "fin_pll" - PLL input clock from XXTI
21+
22+
Required Properties for Clock Controller:
23+
24+
- compatible: clock controllers will use one of the following
25+
compatible strings to indicate the clock controller
26+
functionality.
27+
28+
- "samsung,exynos7-clock-topc"
29+
- "samsung,exynos7-clock-top0"
30+
- "samsung,exynos7-clock-top1"
31+
- "samsung,exynos7-clock-ccore"
32+
- "samsung,exynos7-clock-peric0"
33+
- "samsung,exynos7-clock-peric1"
34+
- "samsung,exynos7-clock-peris"
35+
- "samsung,exynos7-clock-fsys0"
36+
- "samsung,exynos7-clock-fsys1"
37+
38+
- reg: physical base address of the controller and the length of
39+
memory mapped region.
40+
41+
- #clock-cells: should be 1.
42+
43+
- clocks: list of clock identifiers which are fed as the input to
44+
the given clock controller. Please refer the next section to
45+
find the input clocks for a given controller.
46+
47+
- clock-names: list of names of clocks which are fed as the input
48+
to the given clock controller.
49+
50+
Input clocks for top0 clock controller:
51+
- fin_pll
52+
- dout_sclk_bus0_pll
53+
- dout_sclk_bus1_pll
54+
- dout_sclk_cc_pll
55+
- dout_sclk_mfc_pll
56+
57+
Input clocks for top1 clock controller:
58+
- fin_pll
59+
- dout_sclk_bus0_pll
60+
- dout_sclk_bus1_pll
61+
- dout_sclk_cc_pll
62+
- dout_sclk_mfc_pll
63+
64+
Input clocks for ccore clock controller:
65+
- fin_pll
66+
- dout_aclk_ccore_133
67+
68+
Input clocks for peric0 clock controller:
69+
- fin_pll
70+
- dout_aclk_peric0_66
71+
- sclk_uart0
72+
73+
Input clocks for peric1 clock controller:
74+
- fin_pll
75+
- dout_aclk_peric1_66
76+
- sclk_uart1
77+
- sclk_uart2
78+
- sclk_uart3
79+
80+
Input clocks for peris clock controller:
81+
- fin_pll
82+
- dout_aclk_peris_66
83+
84+
Input clocks for fsys0 clock controller:
85+
- fin_pll
86+
- dout_aclk_fsys0_200
87+
- dout_sclk_mmc2
88+
89+
Input clocks for fsys1 clock controller:
90+
- fin_pll
91+
- dout_aclk_fsys1_200
92+
- dout_sclk_mmc0
93+
- dout_sclk_mmc1

‎Documentation/devicetree/bindings/clock/marvell,mmp2.txt

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
* Marvell MMP2 Clock Controller
2+
3+
The MMP2 clock subsystem generates and supplies clock to various
4+
controllers within the MMP2 SoC.
5+
6+
Required Properties:
7+
8+
- compatible: should be one of the following.
9+
- "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
10+
11+
- reg: physical base address of the clock subsystem and length of memory mapped
12+
region. There are 3 places in SOC has clock control logic:
13+
"mpmu", "apmu", "apbc". So three reg spaces need to be defined.
14+
15+
- #clock-cells: should be 1.
16+
- #reset-cells: should be 1.
17+
18+
Each clock is assigned an identifier and client nodes use this identifier
19+
to specify the clock which they consume.
20+
21+
All these identifier could be found in <dt-bindings/clock/marvell-mmp2.h>.

‎Documentation/devicetree/bindings/clock/marvell,pxa168.txt

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
* Marvell PXA168 Clock Controller
2+
3+
The PXA168 clock subsystem generates and supplies clock to various
4+
controllers within the PXA168 SoC.
5+
6+
Required Properties:
7+
8+
- compatible: should be one of the following.
9+
- "marvell,pxa168-clock" - controller compatible with PXA168 SoC.
10+
11+
- reg: physical base address of the clock subsystem and length of memory mapped
12+
region. There are 3 places in SOC has clock control logic:
13+
"mpmu", "apmu", "apbc". So three reg spaces need to be defined.
14+
15+
- #clock-cells: should be 1.
16+
- #reset-cells: should be 1.
17+
18+
Each clock is assigned an identifier and client nodes use this identifier
19+
to specify the clock which they consume.
20+
21+
All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>.

‎Documentation/devicetree/bindings/clock/marvell,pxa910.txt

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@@ -0,0 +1,21 @@
1+
* Marvell PXA910 Clock Controller
2+
3+
The PXA910 clock subsystem generates and supplies clock to various
4+
controllers within the PXA910 SoC.
5+
6+
Required Properties:
7+
8+
- compatible: should be one of the following.
9+
- "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
10+
11+
- reg: physical base address of the clock subsystem and length of memory mapped
12+
region. There are 4 places in SOC has clock control logic:
13+
"mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
14+
15+
- #clock-cells: should be 1.
16+
- #reset-cells: should be 1.
17+
18+
Each clock is assigned an identifier and client nodes use this identifier
19+
to specify the clock which they consume.
20+
21+
All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.

‎Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,22 +7,28 @@ to 64.
77
Required Properties:
88

99
- compatible: Must be one of the following
10+
- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
11+
- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
1012
- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
1113
- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
14+
- "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
1215
- "renesas,cpg-div6-clock" for generic DIV6 clocks
1316
- reg: Base address and length of the memory resource used by the DIV6 clock
14-
- clocks: Reference to the parent clock
17+
- clocks: Reference to the parent clock(s); either one, four, or eight
18+
clocks must be specified. For clocks with multiple parents, invalid
19+
settings must be specified as "<0>".
1520
- #clock-cells: Must be 0
1621
- clock-output-names: The name of the clock as a free-form string
1722

1823

1924
Example
2025
-------
2126

22-
sd2_clk: sd2_clk@e6150078 {
23-
compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
24-
reg = <0 0xe6150078 0 4>;
25-
clocks = <&pll1_div2_clk>;
27+
sdhi2_clk: sdhi2_clk@e615007c {
28+
compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
29+
reg = <0 0xe615007c 0 4>;
30+
clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
31+
<0>, <&extal2_clk>;
2632
#clock-cells = <0>;
27-
clock-output-names = "sd2";
33+
clock-output-names = "sdhi2ck";
2834
};

‎Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -26,11 +26,11 @@ Required Properties:
2626
must appear in the same order as the output clocks.
2727
- #clock-cells: Must be 1
2828
- clock-output-names: The name of the clocks as free-form strings
29-
- renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
29+
- clock-indices: Indices of the gate clocks into the group (0 to 31)
3030

31-
The clocks, clock-output-names and renesas,clock-indices properties contain one
32-
entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
33-
gate clocks must not be declared.
31+
The clocks, clock-output-names and clock-indices properties contain one entry
32+
per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
33+
clocks must not be declared.
3434

3535

3636
Example

‎Documentation/devicetree/bindings/clock/sunxi.txt

Lines changed: 27 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,14 +10,17 @@ Required properties:
1010
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
1111
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
1212
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
13+
"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
1314
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
1415
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
1516
"allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
17+
"allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
1618
"allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
1719
"allwinner,sun4i-a10-axi-clk" - for the AXI clock
1820
"allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
1921
"allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
2022
"allwinner,sun4i-a10-ahb-clk" - for the AHB clock
23+
"allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
2124
"allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
2225
"allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
2326
"allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
@@ -26,24 +29,29 @@ Required properties:
2629
"allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
2730
"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
2831
"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
32+
"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
33+
"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
34+
"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
2935
"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
3036
"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
3137
"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
38+
"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
3239
"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
3340
"allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
3441
"allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
3542
"allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
3643
"allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
3744
"allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
45+
"allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
3846
"allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
39-
"allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
47+
"allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
4048
"allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
4149
"allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
4250
"allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
4351
"allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
4452
"allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
4553
"allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
46-
"allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
54+
"allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
4755
"allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
4856
"allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
4957
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
@@ -63,8 +71,9 @@ Required properties for all clocks:
6371
multiplexed clocks, the list order must match the hardware
6472
programming order.
6573
- #clock-cells : from common clock binding; shall be set to 0 except for
66-
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
67-
"allwinner,sun4i-pll6-clk" where it shall be set to 1
74+
the following compatibles where it shall be set to 1:
75+
"allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
76+
"allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"
6877
- clock-output-names : shall be the corresponding names of the outputs.
6978
If the clock module only has one output, the name shall be the
7079
module name.
@@ -79,6 +88,12 @@ Clock consumers should specify the desired clocks they use with a
7988
"clocks" phandle cell. Consumers that are using a gated clock should
8089
provide an additional ID in their clock property. This ID is the
8190
offset of the bit controlling this particular gate in the register.
91+
For the other clocks with "#clock-cells" = 1, the additional ID shall
92+
refer to the index of the output.
93+
94+
For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
95+
is the normal PLL6 output, or "pll6". The second output is rate doubled
96+
PLL6, or "pll6x2".
8297

8398
For example:
8499

@@ -106,6 +121,14 @@ pll5: clk@01c20020 {
106121
clock-output-names = "pll5_ddr", "pll5_other";
107122
};
108123

124+
pll6: clk@01c20028 {
125+
#clock-cells = <1>;
126+
compatible = "allwinner,sun6i-a31-pll6-clk";
127+
reg = <0x01c20028 0x4>;
128+
clocks = <&osc24M>;
129+
clock-output-names = "pll6", "pll6x2";
130+
};
131+
109132
cpu: cpu@01c20054 {
110133
#clock-cells = <0>;
111134
compatible = "allwinner,sun4i-a10-cpu-clk";

‎MAINTAINERS

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2576,8 +2576,9 @@ F: drivers/media/platform/coda/
25762576

25772577
COMMON CLK FRAMEWORK
25782578
M: Mike Turquette <mturquette@linaro.org>
2579+
M: Stephen Boyd <sboyd@codeaurora.org>
25792580
L: linux-kernel@vger.kernel.org
2580-
T: git git://git.linaro.org/people/mturquette/linux.git
2581+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
25812582
S: Maintained
25822583
F: drivers/clk/
25832584
X: drivers/clk/clkdev.c

‎arch/arm/boot/dts/Makefile

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,9 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
177177
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
178178
dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
179179
dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb
180+
dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \
181+
pxa910-dkb.dtb \
182+
mmp2-brownstone.dtb
180183
dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
181184
dtb-$(CONFIG_ARCH_MXC) += \
182185
imx1-ads.dtb \

‎arch/arm/boot/dts/mmp2-brownstone.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
*/
99

1010
/dts-v1/;
11-
/include/ "mmp2.dtsi"
11+
#include "mmp2.dtsi"
1212

1313
/ {
1414
model = "Marvell MMP2 Brownstone Development Board";

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