Skip to content

Commit c51f716

Browse files
airliedairlied
committed
Merge tag 'drm-intel-next-2014-07-11' of git://anongit.freedesktop.org/drm-intel into drm-next
- fbc improvements when stolen memory is tight (Ben) - cdclk handling improvements for vlv/chv (Ville) - proper fix for stuck primary planes on gmch platforms with cxsr (Imre&Ebgert Eich) - gen8 hw semaphore support (Ben) - more execlist prep work from Oscar Mateo - locking fixes for primary planes (Matt Roper) - code rework to support runtime pm for dpms on hsw/bdw (Paulo, Imre & me), but not yet enabled because some fixes from Paulo haven't made the cut - more gpu boost tuning from Chris - as usual piles of little things all over * tag 'drm-intel-next-2014-07-11' of git://anongit.freedesktop.org/drm-intel: (93 commits) drm/i915: Make the RPS interrupt generation mask handle the vlv wa drm/i915: Move RPS evaluation interval counters to i915->rps drm/i915: Don't cast a pointer to void* unnecessarily drm/i915: don't read LVDS regs at compute_config time drm/i915: check the power domains in intel_lvds_get_hw_state() drm/i915: check the power domains in ironlake_get_pipe_config() drm/i915: don't skip shared DPLL assertion on LPT drm/i915: Only touch WRPLL hw state in enable/disable hooks drm/i915: Switch to common shared dpll framework for WRPLLs drm/i915: ->enable hook for WRPLLs drm/i915: ->disable hook for WRPLLs drm/i915: State readout support for WRPLLs drm/i915: add POWER_DOMAIN_PLLS drm/i915: Document that the pll->mode_set hook is optional drm/i915: Basic shared dpll support for WRPLLs drm/i915: Precompute static ddi_pll_sel values in encoders drm/i915: BDW also has special-purpose DP DDI clocks drm/i915: State readout and cross-checking for ddi_pll_sel drm/i915: Move ddi_pll_sel into the pipe config drm/i915: Add a debugfs file for the shared dpll state ...
2 parents b957f45 + 7b3c29f commit c51f716

23 files changed

+2000
-1246
lines changed

‎drivers/gpu/drm/i915/i915_debugfs.c

Lines changed: 183 additions & 118 deletions
Large diffs are not rendered by default.

‎drivers/gpu/drm/i915/i915_dma.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1593,7 +1593,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
15931593
if (dev_priv == NULL)
15941594
return -ENOMEM;
15951595

1596-
dev->dev_private = (void *)dev_priv;
1596+
dev->dev_private = dev_priv;
15971597
dev_priv->dev = dev;
15981598

15991599
/* copy initial configuration to dev_priv->info */
@@ -1954,11 +1954,11 @@ void i915_driver_lastclose(struct drm_device *dev)
19541954
i915_dma_cleanup(dev);
19551955
}
19561956

1957-
void i915_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
1957+
void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
19581958
{
19591959
mutex_lock(&dev->struct_mutex);
1960-
i915_gem_context_close(dev, file_priv);
1961-
i915_gem_release(dev, file_priv);
1960+
i915_gem_context_close(dev, file);
1961+
i915_gem_release(dev, file);
19621962
mutex_unlock(&dev->struct_mutex);
19631963
}
19641964

‎drivers/gpu/drm/i915/i915_drv.c

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -477,10 +477,6 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
477477
if (i915.semaphores >= 0)
478478
return i915.semaphores;
479479

480-
/* Until we get further testing... */
481-
if (IS_GEN8(dev))
482-
return false;
483-
484480
#ifdef CONFIG_INTEL_IOMMU
485481
/* Enable semaphores on SNB when IO remapping is off */
486482
if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
@@ -520,6 +516,8 @@ static int i915_drm_freeze(struct drm_device *dev)
520516
return error;
521517
}
522518

519+
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
520+
523521
intel_runtime_pm_disable_interrupts(dev);
524522

525523
intel_suspend_gt_powersave(dev);
@@ -541,10 +539,11 @@ static int i915_drm_freeze(struct drm_device *dev)
541539

542540
i915_save_state(dev);
543541

544-
if (acpi_target_system_state() >= ACPI_STATE_S3)
545-
opregion_target_state = PCI_D3cold;
546-
else
542+
opregion_target_state = PCI_D3cold;
543+
#if IS_ENABLED(CONFIG_ACPI_SLEEP)
544+
if (acpi_target_system_state() < ACPI_STATE_S3)
547545
opregion_target_state = PCI_D1;
546+
#endif
548547
intel_opregion_notify_adapter(dev, opregion_target_state);
549548

550549
intel_uncore_forcewake_reset(dev, false);

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 59 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,7 @@ enum intel_display_power_domain {
129129
POWER_DOMAIN_PORT_OTHER,
130130
POWER_DOMAIN_VGA,
131131
POWER_DOMAIN_AUDIO,
132+
POWER_DOMAIN_PLLS,
132133
POWER_DOMAIN_INIT,
133134

134135
POWER_DOMAIN_NUM,
@@ -184,8 +185,10 @@ struct i915_mmu_object;
184185
enum intel_dpll_id {
185186
DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
186187
/* real shared dpll ids must be >= 0 */
187-
DPLL_ID_PCH_PLL_A,
188-
DPLL_ID_PCH_PLL_B,
188+
DPLL_ID_PCH_PLL_A = 0,
189+
DPLL_ID_PCH_PLL_B = 1,
190+
DPLL_ID_WRPLL1 = 0,
191+
DPLL_ID_WRPLL2 = 1,
189192
};
190193
#define I915_NUM_PLLS 2
191194

@@ -194,6 +197,7 @@ struct intel_dpll_hw_state {
194197
uint32_t dpll_md;
195198
uint32_t fp0;
196199
uint32_t fp1;
200+
uint32_t wrpll;
197201
};
198202

199203
struct intel_shared_dpll {
@@ -204,6 +208,8 @@ struct intel_shared_dpll {
204208
/* should match the index in the dev_priv->shared_dplls array */
205209
enum intel_dpll_id id;
206210
struct intel_dpll_hw_state hw_state;
211+
/* The mode_set hook is optional and should be used together with the
212+
* intel_prepare_shared_dpll function. */
207213
void (*mode_set)(struct drm_i915_private *dev_priv,
208214
struct intel_shared_dpll *pll);
209215
void (*enable)(struct drm_i915_private *dev_priv,
@@ -228,12 +234,6 @@ void intel_link_compute_m_n(int bpp, int nlanes,
228234
int pixel_clock, int link_clock,
229235
struct intel_link_m_n *m_n);
230236

231-
struct intel_ddi_plls {
232-
int spll_refcount;
233-
int wrpll1_refcount;
234-
int wrpll2_refcount;
235-
};
236-
237237
/* Interface history:
238238
*
239239
* 1.1: Original.
@@ -324,6 +324,7 @@ struct drm_i915_error_state {
324324
u64 fence[I915_MAX_NUM_FENCES];
325325
struct intel_overlay_error_state *overlay;
326326
struct intel_display_error_state *display;
327+
struct drm_i915_error_object *semaphore_obj;
327328

328329
struct drm_i915_error_ring {
329330
bool valid;
@@ -584,27 +585,48 @@ struct i915_ctx_hang_stats {
584585
};
585586

586587
/* This must match up with the value previously used for execbuf2.rsvd1. */
587-
#define DEFAULT_CONTEXT_ID 0
588+
#define DEFAULT_CONTEXT_HANDLE 0
589+
/**
590+
* struct intel_context - as the name implies, represents a context.
591+
* @ref: reference count.
592+
* @user_handle: userspace tracking identity for this context.
593+
* @remap_slice: l3 row remapping information.
594+
* @file_priv: filp associated with this context (NULL for global default
595+
* context).
596+
* @hang_stats: information about the role of this context in possible GPU
597+
* hangs.
598+
* @vm: virtual memory space used by this context.
599+
* @legacy_hw_ctx: render context backing object and whether it is correctly
600+
* initialized (legacy ring submission mechanism only).
601+
* @link: link in the global list of contexts.
602+
*
603+
* Contexts are memory images used by the hardware to store copies of their
604+
* internal state.
605+
*/
588606
struct intel_context {
589607
struct kref ref;
590-
int id;
591-
bool is_initialized;
608+
int user_handle;
592609
uint8_t remap_slice;
593610
struct drm_i915_file_private *file_priv;
594-
struct drm_i915_gem_object *obj;
595611
struct i915_ctx_hang_stats hang_stats;
596612
struct i915_address_space *vm;
597613

614+
struct {
615+
struct drm_i915_gem_object *rcs_state;
616+
bool initialized;
617+
} legacy_hw_ctx;
618+
598619
struct list_head link;
599620
};
600621

601622
struct i915_fbc {
602623
unsigned long size;
624+
unsigned threshold;
603625
unsigned int fb_id;
604626
enum plane plane;
605627
int y;
606628

607-
struct drm_mm_node *compressed_fb;
629+
struct drm_mm_node compressed_fb;
608630
struct drm_mm_node *compressed_llb;
609631

610632
struct intel_fbc_work {
@@ -880,6 +902,12 @@ struct vlv_s0ix_state {
880902
u32 clock_gate_dis2;
881903
};
882904

905+
struct intel_rps_ei {
906+
u32 cz_clock;
907+
u32 render_c0;
908+
u32 media_c0;
909+
};
910+
883911
struct intel_gen6_power_mgmt {
884912
/* work and pm_iir are protected by dev_priv->irq_lock */
885913
struct work_struct work;
@@ -904,12 +932,17 @@ struct intel_gen6_power_mgmt {
904932
u8 rp1_freq; /* "less than" RP0 power/freqency */
905933
u8 rp0_freq; /* Non-overclocked max frequency. */
906934

935+
u32 ei_interrupt_count;
936+
907937
int last_adj;
908938
enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
909939

910940
bool enabled;
911941
struct delayed_work delayed_resume_work;
912942

943+
/* manual wa residency calculations */
944+
struct intel_rps_ei up_ei, down_ei;
945+
913946
/*
914947
* Protects RPS/RC6 register access and PCU communication.
915948
* Must be taken after struct_mutex if nested.
@@ -1374,6 +1407,7 @@ struct drm_i915_private {
13741407

13751408
struct pci_dev *bridge_dev;
13761409
struct intel_engine_cs ring[I915_NUM_RINGS];
1410+
struct drm_i915_gem_object *semaphore_obj;
13771411
uint32_t last_seqno, next_seqno;
13781412

13791413
drm_dma_handle_t *status_page_dmah;
@@ -1480,7 +1514,6 @@ struct drm_i915_private {
14801514

14811515
int num_shared_dpll;
14821516
struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1483-
struct intel_ddi_plls ddi_plls;
14841517
int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
14851518

14861519
/* Reclocking support */
@@ -1557,6 +1590,11 @@ struct drm_i915_private {
15571590

15581591
struct i915_runtime_pm pm;
15591592

1593+
struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1594+
u32 long_hpd_port_mask;
1595+
u32 short_hpd_port_mask;
1596+
struct work_struct dig_port_work;
1597+
15601598
/* Old dri1 support infrastructure, beware the dragons ya fools entering
15611599
* here! */
15621600
struct i915_dri1_state dri1;
@@ -2097,12 +2135,12 @@ void i915_update_dri1_breadcrumb(struct drm_device *dev);
20972135
extern void i915_kernel_lost_context(struct drm_device * dev);
20982136
extern int i915_driver_load(struct drm_device *, unsigned long flags);
20992137
extern int i915_driver_unload(struct drm_device *);
2100-
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
2138+
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
21012139
extern void i915_driver_lastclose(struct drm_device * dev);
21022140
extern void i915_driver_preclose(struct drm_device *dev,
2103-
struct drm_file *file_priv);
2141+
struct drm_file *file);
21042142
extern void i915_driver_postclose(struct drm_device *dev,
2105-
struct drm_file *file_priv);
2143+
struct drm_file *file);
21062144
extern int i915_driver_device_is_agp(struct drm_device * dev);
21072145
#ifdef CONFIG_COMPAT
21082146
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
@@ -2457,7 +2495,7 @@ static inline void i915_gem_context_unreference(struct intel_context *ctx)
24572495

24582496
static inline bool i915_gem_context_is_default(const struct intel_context *c)
24592497
{
2460-
return c->id == DEFAULT_CONTEXT_ID;
2498+
return c->user_handle == DEFAULT_CONTEXT_HANDLE;
24612499
}
24622500

24632501
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
@@ -2488,7 +2526,7 @@ static inline void i915_gem_chipset_flush(struct drm_device *dev)
24882526

24892527
/* i915_gem_stolen.c */
24902528
int i915_gem_init_stolen(struct drm_device *dev);
2491-
int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2529+
int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
24922530
void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
24932531
void i915_gem_cleanup_stolen(struct drm_device *dev);
24942532
struct drm_i915_gem_object *
@@ -2647,6 +2685,8 @@ extern void gen6_set_rps(struct drm_device *dev, u8 val);
26472685
extern void valleyview_set_rps(struct drm_device *dev, u8 val);
26482686
extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
26492687
extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2688+
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2689+
bool enable);
26502690
extern void intel_detect_pch(struct drm_device *dev);
26512691
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
26522692
extern int intel_enable_rc6(const struct drm_device *dev);

‎drivers/gpu/drm/i915/i915_gem.c

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1168,7 +1168,7 @@ static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
11681168

11691169
timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
11701170

1171-
if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
1171+
if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
11721172
gen6_rps_boost(dev_priv);
11731173
if (file_priv)
11741174
mod_delayed_work(dev_priv->wq,
@@ -2330,7 +2330,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
23302330
u32 request_ring_position, request_start;
23312331
int ret;
23322332

2333-
request_start = intel_ring_get_tail(ring);
2333+
request_start = intel_ring_get_tail(ring->buffer);
23342334
/*
23352335
* Emit any outstanding flushes - execbuf can fail to emit the flush
23362336
* after having emitted the batchbuffer command. Hence we need to fix
@@ -2351,7 +2351,7 @@ int __i915_add_request(struct intel_engine_cs *ring,
23512351
* GPU processing the request, we never over-estimate the
23522352
* position of the head.
23532353
*/
2354-
request_ring_position = intel_ring_get_tail(ring);
2354+
request_ring_position = intel_ring_get_tail(ring->buffer);
23552355

23562356
ret = ring->add_request(ring);
23572357
if (ret)
@@ -2842,6 +2842,8 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj,
28422842
idx = intel_ring_sync_index(from, to);
28432843

28442844
seqno = obj->last_read_seqno;
2845+
/* Optimization: Avoid semaphore sync when we are sure we already
2846+
* waited for an object with higher seqno */
28452847
if (seqno <= from->semaphore.sync_seqno[idx])
28462848
return 0;
28472849

0 commit comments

Comments
 (0)