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Mani-SadhasivamMani-Sadhasivam
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arm64: dts: bitmain: Add BM1880 SoC support
Add devicetree support for Bitmain BM1880 SoC, consisting of a Dual core ARM Cortex A53 subsystem, a Single core RISC-V subsystem and a Tensor Processor subsystem. Only ARM Cortex A53 Application processor subsystem support is enabled for now. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
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‎arch/arm64/boot/dts/Makefile

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@@ -7,6 +7,7 @@ subdir-y += amd
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subdir-y += amlogic
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subdir-y += apm
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subdir-y += arm
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subdir-y += bitmain
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subdir-y += broadcom
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subdir-y += cavium
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subdir-y += exynos

‎arch/arm64/boot/dts/bitmain/bm1880.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2019 Linaro Ltd.
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "bitmain,bm1880";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x1>;
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enable-method = "psci";
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secmon@100000000 {
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reg = <0x1 0x00000000 0x0 0x20000>;
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no-map;
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};
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jpu@130000000 {
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reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
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no-map;
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};
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vpu@138000000 {
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reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
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no-map;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@50001000 {
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compatible = "arm,gic-400";
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reg = <0x0 0x50001000 0x0 0x1000>,
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<0x0 0x50002000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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uart0: serial@58018000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x58018000 0x0 0x2000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@5801A000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x5801a000 0x0 0x2000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@5801C000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x5801c000 0x0 0x2000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@5801E000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x0 0x5801e000 0x0 0x2000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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};
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};

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