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reset: imx7: Add support for i.MX8MQ IP block variant
Add bits and pieces needed to support IP block variant found on i.MX8MQ SoCs. Cc: p.zabel@pengutronix.de Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [p.zabel@pengutronix.de: fixed whitespace alignment] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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‎drivers/reset/Kconfig

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,9 +56,9 @@ config RESET_HSDK
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This enables the reset controller driver for HSDK board.
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config RESET_IMX7
59-
bool "i.MX7 Reset Driver" if COMPILE_TEST
59+
bool "i.MX7/8 Reset Driver" if COMPILE_TEST
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depends on HAS_IOMEM
61-
default SOC_IMX7D
61+
default SOC_IMX7D || (ARM64 && ARCH_MXC)
6262
select MFD_SYSCON
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help
6464
This enables the reset controller driver for i.MX7 SoCs.

‎drivers/reset/reset-imx7.c

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222
#include <linux/reset-controller.h>
2323
#include <linux/regmap.h>
2424
#include <dt-bindings/reset/imx7-reset.h>
25+
#include <dt-bindings/reset/imx8mq-reset.h>
2526

2627
struct imx7_src_signal {
2728
unsigned int offset, bit;
@@ -140,6 +141,126 @@ static const struct imx7_src_variant variant_imx7 = {
140141
},
141142
};
142143

144+
enum imx8mq_src_registers {
145+
SRC_A53RCR0 = 0x0004,
146+
SRC_HDMI_RCR = 0x0030,
147+
SRC_DISP_RCR = 0x0034,
148+
SRC_GPU_RCR = 0x0040,
149+
SRC_VPU_RCR = 0x0044,
150+
SRC_PCIE2_RCR = 0x0048,
151+
SRC_MIPIPHY1_RCR = 0x004c,
152+
SRC_MIPIPHY2_RCR = 0x0050,
153+
SRC_DDRC2_RCR = 0x1004,
154+
};
155+
156+
static const struct imx7_src_signal imx8mq_src_signals[IMX8MQ_RESET_NUM] = {
157+
[IMX8MQ_RESET_A53_CORE_POR_RESET0] = { SRC_A53RCR0, BIT(0) },
158+
[IMX8MQ_RESET_A53_CORE_POR_RESET1] = { SRC_A53RCR0, BIT(1) },
159+
[IMX8MQ_RESET_A53_CORE_POR_RESET2] = { SRC_A53RCR0, BIT(2) },
160+
[IMX8MQ_RESET_A53_CORE_POR_RESET3] = { SRC_A53RCR0, BIT(3) },
161+
[IMX8MQ_RESET_A53_CORE_RESET0] = { SRC_A53RCR0, BIT(4) },
162+
[IMX8MQ_RESET_A53_CORE_RESET1] = { SRC_A53RCR0, BIT(5) },
163+
[IMX8MQ_RESET_A53_CORE_RESET2] = { SRC_A53RCR0, BIT(6) },
164+
[IMX8MQ_RESET_A53_CORE_RESET3] = { SRC_A53RCR0, BIT(7) },
165+
[IMX8MQ_RESET_A53_DBG_RESET0] = { SRC_A53RCR0, BIT(8) },
166+
[IMX8MQ_RESET_A53_DBG_RESET1] = { SRC_A53RCR0, BIT(9) },
167+
[IMX8MQ_RESET_A53_DBG_RESET2] = { SRC_A53RCR0, BIT(10) },
168+
[IMX8MQ_RESET_A53_DBG_RESET3] = { SRC_A53RCR0, BIT(11) },
169+
[IMX8MQ_RESET_A53_ETM_RESET0] = { SRC_A53RCR0, BIT(12) },
170+
[IMX8MQ_RESET_A53_ETM_RESET1] = { SRC_A53RCR0, BIT(13) },
171+
[IMX8MQ_RESET_A53_ETM_RESET2] = { SRC_A53RCR0, BIT(14) },
172+
[IMX8MQ_RESET_A53_ETM_RESET3] = { SRC_A53RCR0, BIT(15) },
173+
[IMX8MQ_RESET_A53_SOC_DBG_RESET] = { SRC_A53RCR0, BIT(20) },
174+
[IMX8MQ_RESET_A53_L2RESET] = { SRC_A53RCR0, BIT(21) },
175+
[IMX8MQ_RESET_SW_NON_SCLR_M4C_RST] = { SRC_M4RCR, BIT(0) },
176+
[IMX8MQ_RESET_OTG1_PHY_RESET] = { SRC_USBOPHY1_RCR, BIT(0) },
177+
[IMX8MQ_RESET_OTG2_PHY_RESET] = { SRC_USBOPHY2_RCR, BIT(0) },
178+
[IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N] = { SRC_MIPIPHY_RCR, BIT(1) },
179+
[IMX8MQ_RESET_MIPI_DSI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(2) },
180+
[IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N] = { SRC_MIPIPHY_RCR, BIT(3) },
181+
[IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N] = { SRC_MIPIPHY_RCR, BIT(4) },
182+
[IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N] = { SRC_MIPIPHY_RCR, BIT(5) },
183+
[IMX8MQ_RESET_PCIEPHY] = { SRC_PCIEPHY_RCR,
184+
BIT(2) | BIT(1) },
185+
[IMX8MQ_RESET_PCIEPHY_PERST] = { SRC_PCIEPHY_RCR, BIT(3) },
186+
[IMX8MQ_RESET_PCIE_CTRL_APPS_EN] = { SRC_PCIEPHY_RCR, BIT(6) },
187+
[IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF] = { SRC_PCIEPHY_RCR, BIT(11) },
188+
[IMX8MQ_RESET_HDMI_PHY_APB_RESET] = { SRC_HDMI_RCR, BIT(0) },
189+
[IMX8MQ_RESET_DISP_RESET] = { SRC_DISP_RCR, BIT(0) },
190+
[IMX8MQ_RESET_GPU_RESET] = { SRC_GPU_RCR, BIT(0) },
191+
[IMX8MQ_RESET_VPU_RESET] = { SRC_VPU_RCR, BIT(0) },
192+
[IMX8MQ_RESET_PCIEPHY2] = { SRC_PCIE2_RCR,
193+
BIT(2) | BIT(1) },
194+
[IMX8MQ_RESET_PCIEPHY2_PERST] = { SRC_PCIE2_RCR, BIT(3) },
195+
[IMX8MQ_RESET_PCIE2_CTRL_APPS_EN] = { SRC_PCIE2_RCR, BIT(6) },
196+
[IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF] = { SRC_PCIE2_RCR, BIT(11) },
197+
[IMX8MQ_RESET_MIPI_CSI1_CORE_RESET] = { SRC_MIPIPHY1_RCR, BIT(0) },
198+
[IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET] = { SRC_MIPIPHY1_RCR, BIT(1) },
199+
[IMX8MQ_RESET_MIPI_CSI1_ESC_RESET] = { SRC_MIPIPHY1_RCR, BIT(2) },
200+
[IMX8MQ_RESET_MIPI_CSI2_CORE_RESET] = { SRC_MIPIPHY2_RCR, BIT(0) },
201+
[IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET] = { SRC_MIPIPHY2_RCR, BIT(1) },
202+
[IMX8MQ_RESET_MIPI_CSI2_ESC_RESET] = { SRC_MIPIPHY2_RCR, BIT(2) },
203+
[IMX8MQ_RESET_DDRC1_PRST] = { SRC_DDRC_RCR, BIT(0) },
204+
[IMX8MQ_RESET_DDRC1_CORE_RESET] = { SRC_DDRC_RCR, BIT(1) },
205+
[IMX8MQ_RESET_DDRC1_PHY_RESET] = { SRC_DDRC_RCR, BIT(2) },
206+
[IMX8MQ_RESET_DDRC2_PHY_RESET] = { SRC_DDRC2_RCR, BIT(0) },
207+
[IMX8MQ_RESET_DDRC2_CORE_RESET] = { SRC_DDRC2_RCR, BIT(1) },
208+
[IMX8MQ_RESET_DDRC2_PRST] = { SRC_DDRC2_RCR, BIT(2) },
209+
};
210+
211+
static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
212+
unsigned long id, bool assert)
213+
{
214+
struct imx7_src *imx7src = to_imx7_src(rcdev);
215+
const unsigned int bit = imx7src->signals[id].bit;
216+
unsigned int value = assert ? bit : 0;
217+
218+
switch (id) {
219+
case IMX8MQ_RESET_PCIEPHY:
220+
case IMX8MQ_RESET_PCIEPHY2: /* fallthrough */
221+
/*
222+
* wait for more than 10us to release phy g_rst and
223+
* btnrst
224+
*/
225+
if (!assert)
226+
udelay(10);
227+
break;
228+
229+
case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
230+
case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN: /* fallthrough */
231+
case IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N: /* fallthrough */
232+
case IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N: /* fallthrough */
233+
case IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N: /* fallthrough */
234+
case IMX8MQ_RESET_MIPI_DSI_RESET_N: /* fallthrough */
235+
case IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N: /* fallthrough */
236+
value = assert ? 0 : bit;
237+
break;
238+
}
239+
240+
return imx7_reset_update(imx7src, id, value);
241+
}
242+
243+
static int imx8mq_reset_assert(struct reset_controller_dev *rcdev,
244+
unsigned long id)
245+
{
246+
return imx8mq_reset_set(rcdev, id, true);
247+
}
248+
249+
static int imx8mq_reset_deassert(struct reset_controller_dev *rcdev,
250+
unsigned long id)
251+
{
252+
return imx8mq_reset_set(rcdev, id, false);
253+
}
254+
255+
static const struct imx7_src_variant variant_imx8mq = {
256+
.signals = imx8mq_src_signals,
257+
.signals_num = ARRAY_SIZE(imx8mq_src_signals),
258+
.ops = {
259+
.assert = imx8mq_reset_assert,
260+
.deassert = imx8mq_reset_deassert,
261+
},
262+
};
263+
143264
static int imx7_reset_probe(struct platform_device *pdev)
144265
{
145266
struct imx7_src *imx7src;
@@ -169,6 +290,7 @@ static int imx7_reset_probe(struct platform_device *pdev)
169290

170291
static const struct of_device_id imx7_reset_dt_ids[] = {
171292
{ .compatible = "fsl,imx7d-src", .data = &variant_imx7 },
293+
{ .compatible = "fsl,imx8mq-src", .data = &variant_imx8mq },
172294
{ /* sentinel */ },
173295
};
174296

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