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Rex Zhualexdeucher
Rex Zhu
authored and
alexdeucher
committed
drm/amd/powerplay: PP/DAL interface changes for dynamic clock switch
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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‎drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c

Lines changed: 57 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -837,78 +837,54 @@ static uint32_t rv_get_mem_latency(struct pp_hwmgr *hwmgr,
837837
return MEM_LATENCY_ERR;
838838
}
839839

840-
static void rv_get_memclocks(struct pp_hwmgr *hwmgr,
840+
static int rv_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
841+
enum amd_pp_clock_type type,
841842
struct pp_clock_levels_with_latency *clocks)
842843
{
843-
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
844-
struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
845-
struct rv_voltage_dependency_table *pmclk_table;
846844
uint32_t i;
847-
848-
pmclk_table = pinfo->vdd_dep_on_mclk;
849-
clocks->num_levels = 0;
850-
851-
for (i = 0; i < pmclk_table->count; i++) {
852-
if (pmclk_table->entries[i].clk) {
853-
clocks->data[clocks->num_levels].clocks_in_khz =
854-
pmclk_table->entries[i].clk;
855-
clocks->data[clocks->num_levels].latency_in_us =
856-
rv_get_mem_latency(hwmgr,
857-
pmclk_table->entries[i].clk);
858-
clocks->num_levels++;
859-
}
860-
}
861-
}
862-
863-
static void rv_get_dcefclocks(struct pp_hwmgr *hwmgr,
864-
struct pp_clock_levels_with_latency *clocks)
865-
{
866845
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
867846
struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
868-
struct rv_voltage_dependency_table *pdcef_table;
869-
uint32_t i;
870-
871-
pdcef_table = pinfo->vdd_dep_on_dcefclk;
872-
for (i = 0; i < pdcef_table->count; i++) {
873-
clocks->data[i].clocks_in_khz = pdcef_table->entries[i].clk;
874-
clocks->data[i].latency_in_us = 0;
875-
}
876-
clocks->num_levels = pdcef_table->count;
877-
}
878-
879-
static void rv_get_socclocks(struct pp_hwmgr *hwmgr,
880-
struct pp_clock_levels_with_latency *clocks)
881-
{
882-
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
883-
struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
884-
struct rv_voltage_dependency_table *psoc_table;
885-
uint32_t i;
886-
887-
psoc_table = pinfo->vdd_dep_on_socclk;
847+
struct rv_voltage_dependency_table *pclk_vol_table;
848+
bool latency_required = false;
888849

889-
for (i = 0; i < psoc_table->count; i++) {
890-
clocks->data[i].clocks_in_khz = psoc_table->entries[i].clk;
891-
clocks->data[i].latency_in_us = 0;
892-
}
893-
clocks->num_levels = psoc_table->count;
894-
}
850+
if (pinfo == NULL)
851+
return -EINVAL;
895852

896-
static int rv_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
897-
enum amd_pp_clock_type type,
898-
struct pp_clock_levels_with_latency *clocks)
899-
{
900853
switch (type) {
901854
case amd_pp_mem_clock:
902-
rv_get_memclocks(hwmgr, clocks);
855+
pclk_vol_table = pinfo->vdd_dep_on_mclk;
856+
latency_required = true;
903857
break;
904-
case amd_pp_dcef_clock:
905-
rv_get_dcefclocks(hwmgr, clocks);
858+
case amd_pp_f_clock:
859+
pclk_vol_table = pinfo->vdd_dep_on_fclk;
860+
latency_required = true;
906861
break;
907-
case amd_pp_soc_clock:
908-
rv_get_socclocks(hwmgr, clocks);
862+
case amd_pp_dcf_clock:
863+
pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
909864
break;
865+
case amd_pp_disp_clock:
866+
pclk_vol_table = pinfo->vdd_dep_on_dispclk;
867+
break;
868+
case amd_pp_phy_clock:
869+
pclk_vol_table = pinfo->vdd_dep_on_phyclk;
870+
break;
871+
case amd_pp_dpp_clock:
872+
pclk_vol_table = pinfo->vdd_dep_on_dppclk;
910873
default:
911-
return -1;
874+
return -EINVAL;
875+
}
876+
877+
if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
878+
return -EINVAL;
879+
880+
clocks->num_levels = 0;
881+
for (i = 0; i < pclk_vol_table->count; i++) {
882+
clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
883+
clocks->data[i].latency_in_us = latency_required ?
884+
rv_get_mem_latency(hwmgr,
885+
pclk_vol_table->entries[i].clk) :
886+
0;
887+
clocks->num_levels++;
912888
}
913889

914890
return 0;
@@ -921,57 +897,64 @@ static int rv_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
921897
uint32_t i;
922898
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
923899
struct rv_clock_voltage_information *pinfo = &(rv_data->clock_vol_info);
924-
struct rv_voltage_dependency_table *pclk_vol_table;
900+
struct rv_voltage_dependency_table *pclk_vol_table = NULL;
901+
902+
if (pinfo == NULL)
903+
return -EINVAL;
925904

926905
switch (type) {
927906
case amd_pp_mem_clock:
928907
pclk_vol_table = pinfo->vdd_dep_on_mclk;
929908
break;
930-
case amd_pp_dcef_clock:
931-
pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
909+
case amd_pp_f_clock:
910+
pclk_vol_table = pinfo->vdd_dep_on_fclk;
932911
break;
933-
case amd_pp_disp_clock:
934-
pclk_vol_table = pinfo->vdd_dep_on_dispclk;
912+
case amd_pp_dcf_clock:
913+
pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
935914
break;
936-
case amd_pp_phy_clock:
937-
pclk_vol_table = pinfo->vdd_dep_on_phyclk;
915+
case amd_pp_soc_clock:
916+
pclk_vol_table = pinfo->vdd_dep_on_socclk;
938917
break;
939-
case amd_pp_dpp_clock:
940-
pclk_vol_table = pinfo->vdd_dep_on_dppclk;
941918
default:
942919
return -EINVAL;
943920
}
944921

945-
if (pclk_vol_table->count == 0)
922+
if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
946923
return -EINVAL;
947924

925+
clocks->num_levels = 0;
948926
for (i = 0; i < pclk_vol_table->count; i++) {
949927
clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
950928
clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
951929
clocks->num_levels++;
952930
}
953931

954-
clocks->num_levels = pclk_vol_table->count;
955-
956932
return 0;
957933
}
958934

959935
int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
960936
struct pp_display_clock_request *clock_req)
961937
{
962938
int result = 0;
939+
struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend);
963940
enum amd_pp_clock_type clk_type = clock_req->clock_type;
964-
uint32_t clk_freq = clock_req->clock_freq_in_khz / 100;
941+
uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
965942
PPSMC_Msg msg;
966943

967944
switch (clk_type) {
968-
case amd_pp_dcef_clock:
945+
case amd_pp_dcf_clock:
946+
if (clk_freq == rv_data->dcf_actual_hard_min_freq)
947+
return 0;
969948
msg = PPSMC_MSG_SetHardMinDcefclkByFreq;
949+
rv_data->dcf_actual_hard_min_freq = clk_freq;
970950
break;
971951
case amd_pp_soc_clock:
972952
msg = PPSMC_MSG_SetHardMinSocclkByFreq;
973953
break;
974-
case amd_pp_mem_clock:
954+
case amd_pp_f_clock:
955+
if (clk_freq == rv_data->f_actual_hard_min_freq)
956+
return 0;
957+
rv_data->f_actual_hard_min_freq = clk_freq;
975958
msg = PPSMC_MSG_SetHardMinFclkByFreq;
976959
break;
977960
default:

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