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drm/i915: Clean up fbc vs. plane checks
Let's record the information whether a plane can do fbc or not under struct inte_plane. v2: Rebase due to i9xx_plane_id Handle BDW/HSW correctly v3: Move inte_fbc_init() back since we depend on it happening even with i915.disable_display, and populate fbc->possible_framebuffer_bits directly from the plane init code instead v4: Add note about plane A being tied to pipe A on HSW+ Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180221173101.19385-1-ville.syrjala@linux.intel.com Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180221160235.11134-5-ville.syrjala@linux.intel.com
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-24
lines changed

3 files changed

+44
-24
lines changed

drivers/gpu/drm/i915/intel_display.c

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13215,6 +13215,32 @@ static const struct drm_plane_funcs intel_cursor_plane_funcs = {
1321513215
.format_mod_supported = intel_cursor_plane_format_mod_supported,
1321613216
};
1321713217

13218+
static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv,
13219+
enum i9xx_plane_id i9xx_plane)
13220+
{
13221+
if (!HAS_FBC(dev_priv))
13222+
return false;
13223+
13224+
if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
13225+
return i9xx_plane == PLANE_A; /* tied to pipe A */
13226+
else if (IS_IVYBRIDGE(dev_priv))
13227+
return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B ||
13228+
i9xx_plane == PLANE_C;
13229+
else if (INTEL_GEN(dev_priv) >= 4)
13230+
return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B;
13231+
else
13232+
return i9xx_plane == PLANE_A;
13233+
}
13234+
13235+
static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
13236+
enum pipe pipe, enum plane_id plane_id)
13237+
{
13238+
if (!HAS_FBC(dev_priv))
13239+
return false;
13240+
13241+
return pipe == PIPE_A && plane_id == PLANE_PRIMARY;
13242+
}
13243+
1321813244
static struct intel_plane *
1321913245
intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
1322013246
{
@@ -13257,6 +13283,21 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
1325713283
primary->i9xx_plane = (enum i9xx_plane_id) pipe;
1325813284
primary->id = PLANE_PRIMARY;
1325913285
primary->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, primary->id);
13286+
13287+
if (INTEL_GEN(dev_priv) >= 9)
13288+
primary->has_fbc = skl_plane_has_fbc(dev_priv,
13289+
primary->pipe,
13290+
primary->id);
13291+
else
13292+
primary->has_fbc = i9xx_plane_has_fbc(dev_priv,
13293+
primary->i9xx_plane);
13294+
13295+
if (primary->has_fbc) {
13296+
struct intel_fbc *fbc = &dev_priv->fbc;
13297+
13298+
fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
13299+
}
13300+
1326013301
primary->check_plane = intel_check_primary_plane;
1326113302

1326213303
if (INTEL_GEN(dev_priv) >= 9) {

drivers/gpu/drm/i915/intel_drv.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -853,6 +853,7 @@ struct intel_plane {
853853
enum plane_id id;
854854
enum pipe pipe;
855855
bool can_scale;
856+
bool has_fbc;
856857
int max_downscale;
857858
uint32_t frontbuffer_bit;
858859

drivers/gpu/drm/i915/intel_fbc.c

Lines changed: 2 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -46,16 +46,6 @@ static inline bool fbc_supported(struct drm_i915_private *dev_priv)
4646
return HAS_FBC(dev_priv);
4747
}
4848

49-
static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
50-
{
51-
return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
52-
}
53-
54-
static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
55-
{
56-
return INTEL_GEN(dev_priv) < 4;
57-
}
58-
5949
static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
6050
{
6151
return INTEL_GEN(dev_priv) <= 3;
@@ -1095,13 +1085,10 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
10951085
struct intel_crtc_state *crtc_state;
10961086
struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc);
10971087

1098-
if (!plane_state->base.visible)
1088+
if (!plane->has_fbc)
10991089
continue;
11001090

1101-
if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
1102-
continue;
1103-
1104-
if (fbc_on_plane_a_only(dev_priv) && plane->i9xx_plane != PLANE_A)
1091+
if (!plane_state->base.visible)
11051092
continue;
11061093

11071094
crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
@@ -1358,7 +1345,6 @@ static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
13581345
void intel_fbc_init(struct drm_i915_private *dev_priv)
13591346
{
13601347
struct intel_fbc *fbc = &dev_priv->fbc;
1361-
enum pipe pipe;
13621348

13631349
INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
13641350
INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
@@ -1379,14 +1365,6 @@ void intel_fbc_init(struct drm_i915_private *dev_priv)
13791365
return;
13801366
}
13811367

1382-
for_each_pipe(dev_priv, pipe) {
1383-
fbc->possible_framebuffer_bits |=
1384-
INTEL_FRONTBUFFER(pipe, PLANE_PRIMARY);
1385-
1386-
if (fbc_on_pipe_a_only(dev_priv))
1387-
break;
1388-
}
1389-
13901368
/* This value was pulled out of someone's hat */
13911369
if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
13921370
I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);

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