Skip to content

Commit cf9b077

Browse files
torvaldstorvalds
committed
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann: "This branch contains platform-related driver updates for ARM and ARM64, these are the areas that bring the changes: New drivers: - driver support for Renesas R-Car V3M (R8A77970) - power management support for Amlogic GX - a new driver for the Tegra BPMP thermal sensor - a new bus driver for Technologic Systems NBUS Changes for subsystems that prefer to merge through arm-soc: - the usual updates for reset controller drivers from Philipp Zabel, with five added drivers for SoCs in the arc, meson, socfpa, uniphier and mediatek families - updates to the ARM SCPI and PSCI frameworks, from Sudeep Holla, Heiner Kallweit and Lorenzo Pieralisi Changes specific to some ARM-based SoC - the Freescale/NXP DPAA QBMan drivers from PowerPC can now work on ARM as well - several changes for power management on Broadcom SoCs - various improvements on Qualcomm, Broadcom, Amlogic, Atmel, Mediatek - minor Cleanups for Samsung, TI OMAP SoCs" [ NOTE! This doesn't work without the previous ARM SoC device-tree pull, because the R8A77970 driver is missing a header file that came from that pull. The fact that this got merged afterwards only fixes it at this point, and bisection of that driver will fail if/when you walk into the history of that driver. - Linus ] * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (96 commits) soc: amlogic: meson-gx-pwrc-vpu: fix power-off when powered by bootloader bus: add driver for the Technologic Systems NBUS memory: omap-gpmc: Remove deprecated gpmc_update_nand_reg() soc: qcom: remove unused label soc: amlogic: gx pm domain: add PM and OF dependencies drivers/firmware: psci_checker: Add missing destroy_timer_on_stack() dt-bindings: power: add amlogic meson power domain bindings soc: amlogic: add Meson GX VPU Domains driver soc: qcom: Remote filesystem memory driver dt-binding: soc: qcom: Add binding for rmtfs memory of: reserved_mem: Accessor for acquiring reserved_mem of/platform: Generalize /reserved-memory handling soc: mediatek: pwrap: fix fatal compiler error soc: mediatek: pwrap: fix compiler errors arm64: mediatek: cleanup message for platform selection soc: Allow test-building of MediaTek drivers soc: mediatek: place Kconfig for all SoC drivers under menu soc: mediatek: pwrap: add support for MT7622 SoC soc: mediatek: pwrap: add common way for setup CS timing extenstion soc: mediatek: pwrap: add MediaTek MT6380 as one slave of pwrap ..
2 parents 527d147 + 339cd0e commit cf9b077

File tree

110 files changed

+6933
-996
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

110 files changed

+6933
-996
lines changed

‎Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,8 @@ Control registers for this memory controller's DDR PHY.
164164

165165
Required properties:
166166
- compatible : should contain one of these
167+
"brcm,brcmstb-ddr-phy-v71.1"
168+
"brcm,brcmstb-ddr-phy-v72.0"
167169
"brcm,brcmstb-ddr-phy-v225.1"
168170
"brcm,brcmstb-ddr-phy-v240.1"
169171
"brcm,brcmstb-ddr-phy-v240.2"
@@ -184,7 +186,9 @@ Sequencer DRAM parameters and control registers. Used for Self-Refresh
184186
Power-Down (SRPD), among other things.
185187

186188
Required properties:
187-
- compatible : should contain "brcm,brcmstb-memc-ddr"
189+
- compatible : should contain one of these
190+
"brcm,brcmstb-memc-ddr-rev-b.2.2"
191+
"brcm,brcmstb-memc-ddr"
188192
- reg : the MEMC DDR register range
189193

190194
Example:

‎Documentation/devicetree/bindings/arm/samsung/pmu.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@ Properties:
44
- compatible : should contain two values. First value must be one from following list:
55
- "samsung,exynos3250-pmu" - for Exynos3250 SoC,
66
- "samsung,exynos4210-pmu" - for Exynos4210 SoC,
7-
- "samsung,exynos4212-pmu" - for Exynos4212 SoC,
87
- "samsung,exynos4412-pmu" - for Exynos4412 SoC,
98
- "samsung,exynos5250-pmu" - for Exynos5250 SoC,
109
- "samsung,exynos5260-pmu" - for Exynos5260 SoC.

‎Documentation/devicetree/bindings/firmware/qcom,scm.txt

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,8 @@ Required properties:
1818
* Core, iface, and bus clocks required for "qcom,scm"
1919
- clock-names: Must contain "core" for the core clock, "iface" for the interface
2020
clock and "bus" for the bus clock per the requirements of the compatible.
21+
- qcom,dload-mode: phandle to the TCSR hardware block and offset of the
22+
download mode control register (optional)
2123

2224
Example for MSM8916:
2325

‎Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
DDR PHY Front End (DPFE) for Broadcom STB
2+
=========================================
3+
4+
DPFE and the DPFE firmware provide an interface for the host CPU to
5+
communicate with the DCPU, which resides inside the DDR PHY.
6+
7+
There are three memory regions for interacting with the DCPU. These are
8+
specified in a single reg property.
9+
10+
Required properties:
11+
- compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu"
12+
or "brcm,dpfe-cpu"
13+
- reg: must reference three register ranges
14+
- start address and length of the DCPU register space
15+
- start address and length of the DCPU data memory space
16+
- start address and length of the DCPU instruction memory space
17+
- reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem";
18+
they must be in the same order as the register declarations
19+
20+
Example:
21+
dpfe_cpu0: dpfe-cpu@f1132000 {
22+
compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu";
23+
reg = <0xf1132000 0x180
24+
0xf1134000 0x1000
25+
0xf1138000 0x4000>;
26+
reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem";
27+
};

‎Documentation/devicetree/bindings/mips/brcm/soc.txt

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,3 +11,156 @@ Required properties:
1111

1212
The experimental -viper variants are for running Linux on the 3384's
1313
BMIPS4355 cable modem CPU instead of the BMIPS5000 application processor.
14+
15+
Power management
16+
----------------
17+
18+
For power management (particularly, S2/S3/S5 system suspend), the following SoC
19+
components are needed:
20+
21+
= Always-On control block (AON CTRL)
22+
23+
This hardware provides control registers for the "always-on" (even in low-power
24+
modes) hardware, such as the Power Management State Machine (PMSM).
25+
26+
Required properties:
27+
- compatible : should be one of
28+
"brcm,bcm7425-aon-ctrl"
29+
"brcm,bcm7429-aon-ctrl"
30+
"brcm,bcm7435-aon-ctrl" and
31+
"brcm,brcmstb-aon-ctrl"
32+
- reg : the register start and length for the AON CTRL block
33+
34+
Example:
35+
36+
syscon@410000 {
37+
compatible = "brcm,bcm7425-aon-ctrl", "brcm,brcmstb-aon-ctrl";
38+
reg = <0x410000 0x400>;
39+
};
40+
41+
= Memory controllers
42+
43+
A Broadcom STB SoC typically has a number of independent memory controllers,
44+
each of which may have several associated hardware blocks, which are versioned
45+
independently (control registers, DDR PHYs, etc.). One might consider
46+
describing these controllers as a parent "memory controllers" block, which
47+
contains N sub-nodes (one for each controller in the system), each of which is
48+
associated with a number of hardware register resources (e.g., its PHY.
49+
50+
== MEMC (MEMory Controller)
51+
52+
Represents a single memory controller instance.
53+
54+
Required properties:
55+
- compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
56+
- ranges : should contain the child address in the parent address
57+
space, must be 0 here, and the register start and length of
58+
the entire memory controller (including all sub nodes: DDR PHY,
59+
arbiter, etc.)
60+
- #address-cells : must be 1
61+
- #size-cells : must be 1
62+
63+
Example:
64+
65+
memory-controller@0 {
66+
compatible = "brcm,brcmstb-memc", "simple-bus";
67+
ranges = <0x0 0x0 0xa000>;
68+
#address-cells = <1>;
69+
#size-cells = <1>;
70+
71+
memc-arb@1000 {
72+
...
73+
};
74+
75+
memc-ddr@2000 {
76+
...
77+
};
78+
79+
ddr-phy@6000 {
80+
...
81+
};
82+
};
83+
84+
Should contain subnodes for any of the following relevant hardware resources:
85+
86+
== DDR PHY control
87+
88+
Control registers for this memory controller's DDR PHY.
89+
90+
Required properties:
91+
- compatible : should contain one of these
92+
"brcm,brcmstb-ddr-phy-v64.5"
93+
"brcm,brcmstb-ddr-phy"
94+
95+
- reg : the DDR PHY register range and length
96+
97+
Example:
98+
99+
ddr-phy@6000 {
100+
compatible = "brcm,brcmstb-ddr-phy-v64.5";
101+
reg = <0x6000 0xc8>;
102+
};
103+
104+
== DDR memory controller sequencer
105+
106+
Control registers for this memory controller's DDR memory sequencer
107+
108+
Required properties:
109+
- compatible : should contain one of these
110+
"brcm,bcm7425-memc-ddr"
111+
"brcm,bcm7429-memc-ddr"
112+
"brcm,bcm7435-memc-ddr" and
113+
"brcm,brcmstb-memc-ddr"
114+
115+
- reg : the DDR sequencer register range and length
116+
117+
Example:
118+
119+
memc-ddr@2000 {
120+
compatible = "brcm,bcm7425-memc-ddr", "brcm,brcmstb-memc-ddr";
121+
reg = <0x2000 0x300>;
122+
};
123+
124+
== MEMC Arbiter
125+
126+
The memory controller arbiter is responsible for memory clients allocation
127+
(bandwidth, priorities etc.) and needs to have its contents restored during
128+
deep sleep states (S3).
129+
130+
Required properties:
131+
132+
- compatible : should contain one of these
133+
"brcm,brcmstb-memc-arb-v10.0.0.0"
134+
"brcm,brcmstb-memc-arb"
135+
136+
- reg : the DDR Arbiter register range and length
137+
138+
Example:
139+
140+
memc-arb@1000 {
141+
compatible = "brcm,brcmstb-memc-arb-v10.0.0.0";
142+
reg = <0x1000 0x248>;
143+
};
144+
145+
== Timers
146+
147+
The Broadcom STB chips contain a timer block with several general purpose
148+
timers that can be used.
149+
150+
Required properties:
151+
152+
- compatible : should contain one of:
153+
"brcm,bcm7425-timers"
154+
"brcm,bcm7429-timers"
155+
"brcm,bcm7435-timers and
156+
"brcm,brcmstb-timers"
157+
- reg : the timers register range
158+
- interrupts : the interrupt line for this timer block
159+
160+
Example:
161+
162+
timers: timer@4067c0 {
163+
compatible = "brcm,bcm7425-timers", "brcm,brcmstb-timers";
164+
reg = <0x4067c0 0x40>;
165+
interrupts = <&periph_intc 19>;
166+
};

‎Documentation/devicetree/bindings/power/amlogic,meson-gx-pwrc.txt

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
1+
Amlogic Meson Power Controller
2+
==============================
3+
4+
The Amlogic Meson SoCs embeds an internal Power domain controller.
5+
6+
VPU Power Domain
7+
----------------
8+
9+
The Video Processing Unit power domain is controlled by this power controller,
10+
but the domain requires some external resources to meet the correct power
11+
sequences.
12+
The bindings must respect the power domain bindings as described in the file
13+
power_domain.txt
14+
15+
Device Tree Bindings:
16+
---------------------
17+
18+
Required properties:
19+
- compatible: should be "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
20+
- #power-domain-cells: should be 0
21+
- amlogic,hhi-sysctrl: phandle to the HHI sysctrl node
22+
- resets: phandles to the reset lines needed for this power demain sequence
23+
as described in ../reset/reset.txt
24+
- clocks: from common clock binding: handle to VPU and VAPB clocks
25+
- clock-names: from common clock binding: must contain "vpu", "vapb"
26+
corresponding to entry in the clocks property.
27+
28+
Parent node should have the following properties :
29+
- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
30+
- reg: base address and size of the AO system control register space.
31+
32+
Example:
33+
-------
34+
35+
ao_sysctrl: sys-ctrl@0 {
36+
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
37+
reg = <0x0 0x0 0x0 0x100>;
38+
39+
pwrc_vpu: power-controller-vpu {
40+
compatible = "amlogic,meson-gx-pwrc-vpu";
41+
#power-domain-cells = <0>;
42+
amlogic,hhi-sysctrl = <&sysctrl>;
43+
resets = <&reset RESET_VIU>,
44+
<&reset RESET_VENC>,
45+
<&reset RESET_VCBUS>,
46+
<&reset RESET_BT656>,
47+
<&reset RESET_DVIN_RESET>,
48+
<&reset RESET_RDMA>,
49+
<&reset RESET_VENCI>,
50+
<&reset RESET_VENCP>,
51+
<&reset RESET_VDAC>,
52+
<&reset RESET_VDI6>,
53+
<&reset RESET_VENCL>,
54+
<&reset RESET_VID_LOCK>;
55+
clocks = <&clkc CLKID_VPU>,
56+
<&clkc CLKID_VAPB>;
57+
clock-names = "vpu", "vapb";
58+
};
59+
};
60+
61+

‎Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ Required properties:
1717
- "renesas,r8a7794-sysc" (R-Car E2)
1818
- "renesas,r8a7795-sysc" (R-Car H3)
1919
- "renesas,r8a7796-sysc" (R-Car M3-W)
20+
- "renesas,r8a77970-sysc" (R-Car V3M)
2021
- "renesas,r8a77995-sysc" (R-Car D3)
2122
- reg: Address start and address range for the device.
2223
- #power-domain-cells: Must be 1.

‎Documentation/devicetree/bindings/reserved-memory/qcom,rmtfs-mem.txt

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
Qualcomm Remote File System Memory binding
2+
3+
This binding describes the Qualcomm remote filesystem memory, which serves the
4+
purpose of describing the shared memory region used for remote processors to
5+
access block device data using the Remote Filesystem protocol.
6+
7+
- compatible:
8+
Usage: required
9+
Value type: <stringlist>
10+
Definition: must be:
11+
"qcom,rmtfs-mem"
12+
13+
- reg:
14+
Usage: required for static allocation
15+
Value type: <prop-encoded-array>
16+
Definition: must specify base address and size of the memory region,
17+
as described in reserved-memory.txt
18+
19+
- size:
20+
Usage: required for dynamic allocation
21+
Value type: <prop-encoded-array>
22+
Definition: must specify a size of the memory region, as described in
23+
reserved-memory.txt
24+
25+
- qcom,client-id:
26+
Usage: required
27+
Value type: <u32>
28+
Definition: identifier of the client to use this region for buffers.
29+
30+
- qcom,vmid:
31+
Usage: optional
32+
Value type: <u32>
33+
Definition: vmid of the remote processor, to set up memory protection.
34+
35+
= EXAMPLE
36+
The following example shows the remote filesystem memory setup for APQ8016,
37+
with the rmtfs region for the Hexagon DSP (id #1) located at 0x86700000.
38+
39+
reserved-memory {
40+
#address-cells = <2>;
41+
#size-cells = <2>;
42+
ranges;
43+
44+
rmtfs@86700000 {
45+
compatible = "qcom,rmtfs-mem";
46+
reg = <0x0 0x86700000 0x0 0xe0000>;
47+
no-map;
48+
49+
qcom,client-id = <1>;
50+
};
51+
};

‎Documentation/devicetree/bindings/reset/renesas,rst.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ Required properties:
2626
- "renesas,r8a7794-rst" (R-Car E2)
2727
- "renesas,r8a7795-rst" (R-Car H3)
2828
- "renesas,r8a7796-rst" (R-Car M3-W)
29+
- "renesas,r8a77970-rst" (R-Car V3M)
2930
- "renesas,r8a77995-rst" (R-Car D3)
3031
- reg: Address start and address range for the device.
3132

‎Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
Binding for the AXS10x reset controller
2+
3+
This binding describes the ARC AXS10x boards custom IP-block which allows
4+
to control reset signals of selected peripherals. For example DW GMAC, etc...
5+
This block is controlled via memory-mapped register (AKA CREG) which
6+
represents up-to 32 reset lines.
7+
8+
As of today only the following lines are used:
9+
- DW GMAC - line 5
10+
11+
This binding uses the common reset binding[1].
12+
13+
[1] Documentation/devicetree/bindings/reset/reset.txt
14+
15+
Required properties:
16+
- compatible: should be "snps,axs10x-reset".
17+
- reg: should always contain pair address - length: for creg reset
18+
bits register.
19+
- #reset-cells: from common reset binding; Should always be set to 1.
20+
21+
Example:
22+
reset: reset-controller@11220 {
23+
compatible = "snps,axs10x-reset";
24+
#reset-cells = <1>;
25+
reg = <0x11220 0x4>;
26+
};
27+
28+
Specifying reset lines connected to IP modules:
29+
ethernet@.... {
30+
....
31+
resets = <&reset 5>;
32+
....
33+
};

0 commit comments

Comments
 (0)