Skip to content

Commit d15ae81

Browse files
torvaldstorvalds
committed
Merge tag 'drm-fixes-for-v4.7-rc8-intel-kbl' of git://people.freedesktop.org/~airlied/linux
Pull intel kabylake drm fixes from Dave Airlie: "As mentioned Intel has gathered all the Kabylake fixes from -next, which we've enabled in 4.7 for the first time, these are pretty much limited in scope to only affects kabylake, which is hw that isn't shipping yet. So I'm mostly okay with it going in now. If we don't land this, it might be a good idea to disable kabylake support in 4.7 before we ship" * tag 'drm-fixes-for-v4.7-rc8-intel-kbl' of git://people.freedesktop.org/~airlied/linux: (28 commits) drm/i915/kbl: Introduce the first official DMC for Kabylake. drm/i915: Introduce Kabypoint PCH for Kabylake H/DT. drm/i915/gen9: implement WaConextSwitchWithConcurrentTLBInvalidate drm/i915/gen9: Add WaFbcHighMemBwCorruptionAvoidance drm/i195/fbc: Add WaFbcNukeOnHostModify drm/i915/gen9: Add WaFbcWakeMemOn drm/i915/gen9: Add WaFbcTurnOffFbcWatermark drm/i915/kbl: Add WaClearSlmSpaceAtContextSwitch drm/i915/gen9: Add WaEnableChickenDCPR drm/i915/kbl: Add WaDisableSbeCacheDispatchPortSharing drm/i915/kbl: Add WaDisableGafsUnitClkGating drm/i915/kbl: Add WaForGAMHang drm/i915: Add WaInsertDummyPushConstP for bxt and kbl drm/i915/kbl: Add WaDisableDynamicCreditSharing drm/i915/kbl: Add WaDisableGamClockGating drm/i915/gen9: Enable must set chicken bits in config0 reg drm/i915/kbl: Add WaDisableLSQCROPERFforOCL drm/i915/kbl: Add WaDisableSDEUnitClockGating drm/i915/kbl: Add WaDisableFenceDestinationToSLM for A0 drm/i915/kbl: Add WaEnableGapsTsvCreditFix ...
2 parents 3f2625d + cad7d8d commit d15ae81

File tree

10 files changed

+295
-61
lines changed

10 files changed

+295
-61
lines changed

‎drivers/gpu/drm/i915/i915_drv.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -512,6 +512,10 @@ void intel_detect_pch(struct drm_device *dev)
512512
DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
513513
WARN_ON(!IS_SKYLAKE(dev) &&
514514
!IS_KABYLAKE(dev));
515+
} else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) {
516+
dev_priv->pch_type = PCH_KBP;
517+
DRM_DEBUG_KMS("Found KabyPoint PCH\n");
518+
WARN_ON(!IS_KABYLAKE(dev));
515519
} else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
516520
(id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
517521
((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -990,6 +990,7 @@ enum intel_pch {
990990
PCH_CPT, /* Cougarpoint PCH */
991991
PCH_LPT, /* Lynxpoint PCH */
992992
PCH_SPT, /* Sunrisepoint PCH */
993+
PCH_KBP, /* Kabypoint PCH */
993994
PCH_NOP,
994995
};
995996

@@ -2600,6 +2601,15 @@ struct drm_i915_cmd_table {
26002601

26012602
#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
26022603

2604+
#define KBL_REVID_A0 0x0
2605+
#define KBL_REVID_B0 0x1
2606+
#define KBL_REVID_C0 0x2
2607+
#define KBL_REVID_D0 0x3
2608+
#define KBL_REVID_E0 0x4
2609+
2610+
#define IS_KBL_REVID(p, since, until) \
2611+
(IS_KABYLAKE(p) && IS_REVID(p, since, until))
2612+
26032613
/*
26042614
* The genX designation typically refers to the render engine, so render
26052615
* capability related checks should use IS_GEN, while display and other checks
@@ -2708,11 +2718,13 @@ struct drm_i915_cmd_table {
27082718
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
27092719
#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
27102720
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2721+
#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
27112722
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
27122723
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
27132724
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
27142725

27152726
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2727+
#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
27162728
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
27172729
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
27182730
#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)

‎drivers/gpu/drm/i915/i915_gem_stolen.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -55,8 +55,10 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
5555
return -ENODEV;
5656

5757
/* See the comment at the drm_mm_init() call for more about this check.
58-
* WaSkipStolenMemoryFirstPage:bdw,chv (incomplete) */
59-
if (INTEL_INFO(dev_priv)->gen == 8 && start < 4096)
58+
* WaSkipStolenMemoryFirstPage:bdw,chv,kbl (incomplete)
59+
*/
60+
if (start < 4096 && (IS_GEN8(dev_priv) ||
61+
IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)))
6062
start = 4096;
6163

6264
mutex_lock(&dev_priv->mm.stolen_lock);

‎drivers/gpu/drm/i915/i915_irq.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2471,7 +2471,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
24712471
I915_WRITE(SDEIIR, iir);
24722472
ret = IRQ_HANDLED;
24732473

2474-
if (HAS_PCH_SPT(dev_priv))
2474+
if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
24752475
spt_irq_handler(dev, iir);
24762476
else
24772477
cpt_irq_handler(dev, iir);
@@ -4661,7 +4661,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
46614661
dev->driver->disable_vblank = gen8_disable_vblank;
46624662
if (IS_BROXTON(dev))
46634663
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4664-
else if (HAS_PCH_SPT(dev))
4664+
else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
46654665
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
46664666
else
46674667
dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -220,6 +220,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
220220
#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
221221
#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
222222

223+
#define GEN8_CONFIG0 _MMIO(0xD00)
224+
#define GEN9_DEFAULT_FIXES (1 << 3 | 1 << 2 | 1 << 1)
225+
223226
#define GAC_ECO_BITS _MMIO(0x14090)
224227
#define ECOBITS_SNB_BIT (1<<13)
225228
#define ECOBITS_PPGTT_CACHE64B (3<<8)
@@ -1669,6 +1672,9 @@ enum skl_disp_power_wells {
16691672

16701673
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
16711674

1675+
#define GAMT_CHKN_BIT_REG _MMIO(0x4ab8)
1676+
#define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
1677+
16721678
#if 0
16731679
#define PRB0_TAIL _MMIO(0x2030)
16741680
#define PRB0_HEAD _MMIO(0x2034)
@@ -1804,6 +1810,10 @@ enum skl_disp_power_wells {
18041810
#define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2))
18051811
#define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2))
18061812

1813+
/* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
1814+
#define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20D4)
1815+
#define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2)
1816+
18071817
/* WaClearTdlStateAckDirtyBits */
18081818
#define GEN8_STATE_ACK _MMIO(0x20F0)
18091819
#define GEN9_STATE_ACK_SLICE1 _MMIO(0x20F8)
@@ -2200,6 +2210,8 @@ enum skl_disp_power_wells {
22002210
#define ILK_DPFC_STATUS _MMIO(0x43210)
22012211
#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
22022212
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
2213+
#define ILK_DPFC_DISABLE_DUMMY0 (1<<8)
2214+
#define ILK_DPFC_NUKE_ON_ANY_MODIFICATION (1<<23)
22032215
#define ILK_FBC_RT_BASE _MMIO(0x2128)
22042216
#define ILK_FBC_RT_VALID (1<<0)
22052217
#define SNB_FBC_FRONT_BUFFER (1<<1)
@@ -6031,6 +6043,7 @@ enum skl_disp_power_wells {
60316043
#define CHICKEN_PAR1_1 _MMIO(0x42080)
60326044
#define DPA_MASK_VBLANK_SRD (1 << 15)
60336045
#define FORCE_ARB_IDLE_PLANES (1 << 14)
6046+
#define SKL_EDP_PSR_FIX_RDWRAP (1 << 3)
60346047

60356048
#define _CHICKEN_PIPESL_1_A 0x420b0
60366049
#define _CHICKEN_PIPESL_1_B 0x420b4
@@ -6039,6 +6052,7 @@ enum skl_disp_power_wells {
60396052
#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
60406053

60416054
#define DISP_ARB_CTL _MMIO(0x45000)
6055+
#define DISP_FBC_MEMORY_WAKE (1<<31)
60426056
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
60436057
#define DISP_FBC_WM_DIS (1<<15)
60446058
#define DISP_ARB_CTL2 _MMIO(0x45004)
@@ -6052,6 +6066,9 @@ enum skl_disp_power_wells {
60526066
#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
60536067
#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
60546068

6069+
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
6070+
#define MASK_WAKEMEM (1<<13)
6071+
60556072
#define SKL_DFSM _MMIO(0x51000)
60566073
#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
60576074
#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
@@ -6069,13 +6086,15 @@ enum skl_disp_power_wells {
60696086
#define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
60706087

60716088
#define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
6089+
#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
60726090
#define GEN8_CS_CHICKEN1 _MMIO(0x2580)
60736091

60746092
/* GEN7 chicken */
60756093
#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
60766094
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
60776095
# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
60786096
#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
6097+
# define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1<<8)
60796098
# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
60806099

60816100
#define HIZ_CHICKEN _MMIO(0x7018)
@@ -6921,6 +6940,7 @@ enum skl_disp_power_wells {
69216940
#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
69226941

69236942
#define GEN6_UCGCTL1 _MMIO(0x9400)
6943+
# define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22)
69246944
# define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16)
69256945
# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
69266946
# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
@@ -6937,6 +6957,7 @@ enum skl_disp_power_wells {
69376957

69386958
#define GEN7_UCGCTL4 _MMIO(0x940c)
69396959
#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
6960+
#define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1<<14)
69406961

69416962
#define GEN6_RCGCTL1 _MMIO(0x9410)
69426963
#define GEN6_RCGCTL2 _MMIO(0x9414)

‎drivers/gpu/drm/i915/intel_csr.c

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -41,16 +41,22 @@
4141
* be moved to FW_FAILED.
4242
*/
4343

44+
#define I915_CSR_KBL "i915/kbl_dmc_ver1.bin"
45+
MODULE_FIRMWARE(I915_CSR_KBL);
46+
#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1)
47+
4448
#define I915_CSR_SKL "i915/skl_dmc_ver1.bin"
49+
MODULE_FIRMWARE(I915_CSR_SKL);
50+
#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
51+
4552
#define I915_CSR_BXT "i915/bxt_dmc_ver1.bin"
53+
MODULE_FIRMWARE(I915_CSR_BXT);
54+
#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
4655

4756
#define FIRMWARE_URL "https://01.org/linuxgraphics/intel-linux-graphics-firmwares"
4857

49-
MODULE_FIRMWARE(I915_CSR_SKL);
50-
MODULE_FIRMWARE(I915_CSR_BXT);
5158

52-
#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 23)
53-
#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
59+
5460

5561
#define CSR_MAX_FW_SIZE 0x2FFF
5662
#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
@@ -169,12 +175,10 @@ struct stepping_info {
169175
char substepping;
170176
};
171177

172-
/*
173-
* Kabylake derivated from Skylake H0, so SKL H0
174-
* is the right firmware for KBL A0 (revid 0).
175-
*/
176178
static const struct stepping_info kbl_stepping_info[] = {
177-
{'H', '0'}, {'I', '0'}
179+
{'A', '0'}, {'B', '0'}, {'C', '0'},
180+
{'D', '0'}, {'E', '0'}, {'F', '0'},
181+
{'G', '0'}, {'H', '0'}, {'I', '0'},
178182
};
179183

180184
static const struct stepping_info skl_stepping_info[] = {
@@ -298,7 +302,9 @@ static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
298302

299303
csr->version = css_header->version;
300304

301-
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
305+
if (IS_KABYLAKE(dev_priv)) {
306+
required_min_version = KBL_CSR_VERSION_REQUIRED;
307+
} else if (IS_SKYLAKE(dev_priv)) {
302308
required_min_version = SKL_CSR_VERSION_REQUIRED;
303309
} else if (IS_BROXTON(dev_priv)) {
304310
required_min_version = BXT_CSR_VERSION_REQUIRED;
@@ -446,7 +452,9 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
446452
if (!HAS_CSR(dev_priv))
447453
return;
448454

449-
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
455+
if (IS_KABYLAKE(dev_priv))
456+
csr->fw_path = I915_CSR_KBL;
457+
else if (IS_SKYLAKE(dev_priv))
450458
csr->fw_path = I915_CSR_SKL;
451459
else if (IS_BROXTON(dev_priv))
452460
csr->fw_path = I915_CSR_BXT;

‎drivers/gpu/drm/i915/intel_lrc.c

Lines changed: 55 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1103,15 +1103,17 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
11031103
uint32_t *const batch,
11041104
uint32_t index)
11051105
{
1106+
struct drm_i915_private *dev_priv = engine->dev->dev_private;
11061107
uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
11071108

11081109
/*
1109-
* WaDisableLSQCROPERFforOCL:skl
1110+
* WaDisableLSQCROPERFforOCL:skl,kbl
11101111
* This WA is implemented in skl_init_clock_gating() but since
11111112
* this batch updates GEN8_L3SQCREG4 with default value we need to
11121113
* set this bit here to retain the WA during flush.
11131114
*/
1114-
if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
1115+
if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) ||
1116+
IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
11151117
l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
11161118

11171119
wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
@@ -1273,6 +1275,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
12731275
{
12741276
int ret;
12751277
struct drm_device *dev = engine->dev;
1278+
struct drm_i915_private *dev_priv = dev->dev_private;
12761279
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
12771280

12781281
/* WaDisableCtxRestoreArbitration:skl,bxt */
@@ -1286,6 +1289,22 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
12861289
return ret;
12871290
index = ret;
12881291

1292+
/* WaClearSlmSpaceAtContextSwitch:kbl */
1293+
/* Actual scratch location is at 128 bytes offset */
1294+
if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
1295+
uint32_t scratch_addr
1296+
= engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1297+
1298+
wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1299+
wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1300+
PIPE_CONTROL_GLOBAL_GTT_IVB |
1301+
PIPE_CONTROL_CS_STALL |
1302+
PIPE_CONTROL_QW_WRITE));
1303+
wa_ctx_emit(batch, index, scratch_addr);
1304+
wa_ctx_emit(batch, index, 0);
1305+
wa_ctx_emit(batch, index, 0);
1306+
wa_ctx_emit(batch, index, 0);
1307+
}
12891308
/* Pad to end of cacheline */
12901309
while (index % CACHELINE_DWORDS)
12911310
wa_ctx_emit(batch, index, MI_NOOP);
@@ -1687,9 +1706,10 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
16871706
struct intel_ringbuffer *ringbuf = request->ringbuf;
16881707
struct intel_engine_cs *engine = ringbuf->engine;
16891708
u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1690-
bool vf_flush_wa = false;
1709+
bool vf_flush_wa = false, dc_flush_wa = false;
16911710
u32 flags = 0;
16921711
int ret;
1712+
int len;
16931713

16941714
flags |= PIPE_CONTROL_CS_STALL;
16951715

@@ -1716,9 +1736,21 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
17161736
*/
17171737
if (IS_GEN9(engine->dev))
17181738
vf_flush_wa = true;
1739+
1740+
/* WaForGAMHang:kbl */
1741+
if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1742+
dc_flush_wa = true;
17191743
}
17201744

1721-
ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
1745+
len = 6;
1746+
1747+
if (vf_flush_wa)
1748+
len += 6;
1749+
1750+
if (dc_flush_wa)
1751+
len += 12;
1752+
1753+
ret = intel_ring_begin(request, len);
17221754
if (ret)
17231755
return ret;
17241756

@@ -1731,12 +1763,31 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
17311763
intel_logical_ring_emit(ringbuf, 0);
17321764
}
17331765

1766+
if (dc_flush_wa) {
1767+
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1768+
intel_logical_ring_emit(ringbuf, PIPE_CONTROL_DC_FLUSH_ENABLE);
1769+
intel_logical_ring_emit(ringbuf, 0);
1770+
intel_logical_ring_emit(ringbuf, 0);
1771+
intel_logical_ring_emit(ringbuf, 0);
1772+
intel_logical_ring_emit(ringbuf, 0);
1773+
}
1774+
17341775
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
17351776
intel_logical_ring_emit(ringbuf, flags);
17361777
intel_logical_ring_emit(ringbuf, scratch_addr);
17371778
intel_logical_ring_emit(ringbuf, 0);
17381779
intel_logical_ring_emit(ringbuf, 0);
17391780
intel_logical_ring_emit(ringbuf, 0);
1781+
1782+
if (dc_flush_wa) {
1783+
intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
1784+
intel_logical_ring_emit(ringbuf, PIPE_CONTROL_CS_STALL);
1785+
intel_logical_ring_emit(ringbuf, 0);
1786+
intel_logical_ring_emit(ringbuf, 0);
1787+
intel_logical_ring_emit(ringbuf, 0);
1788+
intel_logical_ring_emit(ringbuf, 0);
1789+
}
1790+
17401791
intel_logical_ring_advance(ringbuf);
17411792

17421793
return 0;

‎drivers/gpu/drm/i915/intel_panel.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1731,7 +1731,8 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel)
17311731
panel->backlight.set = bxt_set_backlight;
17321732
panel->backlight.get = bxt_get_backlight;
17331733
panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
1734-
} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv)) {
1734+
} else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
1735+
HAS_PCH_KBP(dev_priv)) {
17351736
panel->backlight.setup = lpt_setup_backlight;
17361737
panel->backlight.enable = lpt_enable_backlight;
17371738
panel->backlight.disable = lpt_disable_backlight;

0 commit comments

Comments
 (0)