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horiagherbertx
horiag
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herbertx
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crypto: caam - add register map changes cf. Era 10
Era 10 changes the register map. The updates that affect the drivers: -new version registers are added -DBG_DBG[deco_state] field is moved to a new register - DBG_EXEC[19:16] @ 8_0E3Ch. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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8 files changed

+184
-49
lines changed

8 files changed

+184
-49
lines changed

‎drivers/crypto/caam/caamalg.c

Lines changed: 33 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -3135,7 +3135,7 @@ static int __init caam_algapi_init(void)
31353135
struct device *ctrldev;
31363136
struct caam_drv_private *priv;
31373137
int i = 0, err = 0;
3138-
u32 cha_vid, cha_inst, des_inst, aes_inst, md_inst;
3138+
u32 aes_vid, aes_inst, des_inst, md_vid, md_inst;
31393139
unsigned int md_limit = SHA512_DIGEST_SIZE;
31403140
bool registered = false;
31413141

@@ -3168,14 +3168,34 @@ static int __init caam_algapi_init(void)
31683168
* Register crypto algorithms the device supports.
31693169
* First, detect presence and attributes of DES, AES, and MD blocks.
31703170
*/
3171-
cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
3172-
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
3173-
des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> CHA_ID_LS_DES_SHIFT;
3174-
aes_inst = (cha_inst & CHA_ID_LS_AES_MASK) >> CHA_ID_LS_AES_SHIFT;
3175-
md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
3171+
if (priv->era < 10) {
3172+
u32 cha_vid, cha_inst;
3173+
3174+
cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
3175+
aes_vid = cha_vid & CHA_ID_LS_AES_MASK;
3176+
md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
3177+
3178+
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
3179+
des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >>
3180+
CHA_ID_LS_DES_SHIFT;
3181+
aes_inst = cha_inst & CHA_ID_LS_AES_MASK;
3182+
md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
3183+
} else {
3184+
u32 aesa, mdha;
3185+
3186+
aesa = rd_reg32(&priv->ctrl->vreg.aesa);
3187+
mdha = rd_reg32(&priv->ctrl->vreg.mdha);
3188+
3189+
aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
3190+
md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
3191+
3192+
des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK;
3193+
aes_inst = aesa & CHA_VER_NUM_MASK;
3194+
md_inst = mdha & CHA_VER_NUM_MASK;
3195+
}
31763196

31773197
/* If MD is present, limit digest size based on LP256 */
3178-
if (md_inst && ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256))
3198+
if (md_inst && md_vid == CHA_VER_VID_MD_LP256)
31793199
md_limit = SHA256_DIGEST_SIZE;
31803200

31813201
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
@@ -3196,10 +3216,10 @@ static int __init caam_algapi_init(void)
31963216
* Check support for AES modes not available
31973217
* on LP devices.
31983218
*/
3199-
if ((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP)
3200-
if ((t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK) ==
3201-
OP_ALG_AAI_XTS)
3202-
continue;
3219+
if (aes_vid == CHA_VER_VID_AES_LP &&
3220+
(t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK) ==
3221+
OP_ALG_AAI_XTS)
3222+
continue;
32033223

32043224
caam_skcipher_alg_init(t_alg);
32053225

@@ -3236,9 +3256,8 @@ static int __init caam_algapi_init(void)
32363256
* Check support for AES algorithms not available
32373257
* on LP devices.
32383258
*/
3239-
if ((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP)
3240-
if (alg_aai == OP_ALG_AAI_GCM)
3241-
continue;
3259+
if (aes_vid == CHA_VER_VID_AES_LP && alg_aai == OP_ALG_AAI_GCM)
3260+
continue;
32423261

32433262
/*
32443263
* Skip algorithms requiring message digests

‎drivers/crypto/caam/caamalg_qi.c

Lines changed: 28 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2462,7 +2462,7 @@ static int __init caam_qi_algapi_init(void)
24622462
struct device *ctrldev;
24632463
struct caam_drv_private *priv;
24642464
int i = 0, err = 0;
2465-
u32 cha_vid, cha_inst, des_inst, aes_inst, md_inst;
2465+
u32 aes_vid, aes_inst, des_inst, md_vid, md_inst;
24662466
unsigned int md_limit = SHA512_DIGEST_SIZE;
24672467
bool registered = false;
24682468

@@ -2497,14 +2497,34 @@ static int __init caam_qi_algapi_init(void)
24972497
* Register crypto algorithms the device supports.
24982498
* First, detect presence and attributes of DES, AES, and MD blocks.
24992499
*/
2500-
cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
2501-
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
2502-
des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >> CHA_ID_LS_DES_SHIFT;
2503-
aes_inst = (cha_inst & CHA_ID_LS_AES_MASK) >> CHA_ID_LS_AES_SHIFT;
2504-
md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
2500+
if (priv->era < 10) {
2501+
u32 cha_vid, cha_inst;
2502+
2503+
cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
2504+
aes_vid = cha_vid & CHA_ID_LS_AES_MASK;
2505+
md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
2506+
2507+
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
2508+
des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >>
2509+
CHA_ID_LS_DES_SHIFT;
2510+
aes_inst = cha_inst & CHA_ID_LS_AES_MASK;
2511+
md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
2512+
} else {
2513+
u32 aesa, mdha;
2514+
2515+
aesa = rd_reg32(&priv->ctrl->vreg.aesa);
2516+
mdha = rd_reg32(&priv->ctrl->vreg.mdha);
2517+
2518+
aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
2519+
md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
2520+
2521+
des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK;
2522+
aes_inst = aesa & CHA_VER_NUM_MASK;
2523+
md_inst = mdha & CHA_VER_NUM_MASK;
2524+
}
25052525

25062526
/* If MD is present, limit digest size based on LP256 */
2507-
if (md_inst && ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256))
2527+
if (md_inst && md_vid == CHA_VER_VID_MD_LP256)
25082528
md_limit = SHA256_DIGEST_SIZE;
25092529

25102530
for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
@@ -2556,8 +2576,7 @@ static int __init caam_qi_algapi_init(void)
25562576
* Check support for AES algorithms not available
25572577
* on LP devices.
25582578
*/
2559-
if (((cha_vid & CHA_ID_LS_AES_MASK) == CHA_ID_LS_AES_LP) &&
2560-
(alg_aai == OP_ALG_AAI_GCM))
2579+
if (aes_vid == CHA_VER_VID_AES_LP && alg_aai == OP_ALG_AAI_GCM)
25612580
continue;
25622581

25632582
/*

‎drivers/crypto/caam/caamhash.c

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
* caam - Freescale FSL CAAM support for ahash functions of crypto API
44
*
55
* Copyright 2011 Freescale Semiconductor, Inc.
6+
* Copyright 2018 NXP
67
*
78
* Based on caamalg.c crypto API driver.
89
*
@@ -1801,7 +1802,7 @@ static int __init caam_algapi_hash_init(void)
18011802
int i = 0, err = 0;
18021803
struct caam_drv_private *priv;
18031804
unsigned int md_limit = SHA512_DIGEST_SIZE;
1804-
u32 cha_inst, cha_vid;
1805+
u32 md_inst, md_vid;
18051806

18061807
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
18071808
if (!dev_node) {
@@ -1831,18 +1832,27 @@ static int __init caam_algapi_hash_init(void)
18311832
* Register crypto algorithms the device supports. First, identify
18321833
* presence and attributes of MD block.
18331834
*/
1834-
cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
1835-
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
1835+
if (priv->era < 10) {
1836+
md_vid = (rd_reg32(&priv->ctrl->perfmon.cha_id_ls) &
1837+
CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
1838+
md_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
1839+
CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
1840+
} else {
1841+
u32 mdha = rd_reg32(&priv->ctrl->vreg.mdha);
1842+
1843+
md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
1844+
md_inst = mdha & CHA_VER_NUM_MASK;
1845+
}
18361846

18371847
/*
18381848
* Skip registration of any hashing algorithms if MD block
18391849
* is not present.
18401850
*/
1841-
if (!((cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT))
1851+
if (!md_inst)
18421852
return -ENODEV;
18431853

18441854
/* Limit digest size based on LP256 */
1845-
if ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256)
1855+
if (md_vid == CHA_VER_VID_MD_LP256)
18461856
md_limit = SHA256_DIGEST_SIZE;
18471857

18481858
INIT_LIST_HEAD(&hash_list);

‎drivers/crypto/caam/caampkc.c

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
* caam - Freescale FSL CAAM support for Public Key Cryptography
44
*
55
* Copyright 2016 Freescale Semiconductor, Inc.
6+
* Copyright 2018 NXP
67
*
78
* There is no Shared Descriptor for PKC so that the Job Descriptor must carry
89
* all the desired key parameters, input and output pointers.
@@ -1017,7 +1018,7 @@ static int __init caam_pkc_init(void)
10171018
struct platform_device *pdev;
10181019
struct device *ctrldev;
10191020
struct caam_drv_private *priv;
1020-
u32 cha_inst, pk_inst;
1021+
u32 pk_inst;
10211022
int err;
10221023

10231024
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
@@ -1045,8 +1046,11 @@ static int __init caam_pkc_init(void)
10451046
return -ENODEV;
10461047

10471048
/* Determine public key hardware accelerator presence. */
1048-
cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
1049-
pk_inst = (cha_inst & CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT;
1049+
if (priv->era < 10)
1050+
pk_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
1051+
CHA_ID_LS_PK_MASK) >> CHA_ID_LS_PK_SHIFT;
1052+
else
1053+
pk_inst = rd_reg32(&priv->ctrl->vreg.pkha) & CHA_VER_NUM_MASK;
10501054

10511055
/* Do not register algorithms if PKHA is not present. */
10521056
if (!pk_inst)

‎drivers/crypto/caam/caamrng.c

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
* caam - Freescale FSL CAAM support for hw_random
44
*
55
* Copyright 2011 Freescale Semiconductor, Inc.
6+
* Copyright 2018 NXP
67
*
78
* Based on caamalg.c crypto API driver.
89
*
@@ -309,6 +310,7 @@ static int __init caam_rng_init(void)
309310
struct platform_device *pdev;
310311
struct device *ctrldev;
311312
struct caam_drv_private *priv;
313+
u32 rng_inst;
312314
int err;
313315

314316
dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
@@ -336,7 +338,13 @@ static int __init caam_rng_init(void)
336338
return -ENODEV;
337339

338340
/* Check for an instantiated RNG before registration */
339-
if (!(rd_reg32(&priv->ctrl->perfmon.cha_num_ls) & CHA_ID_LS_RNG_MASK))
341+
if (priv->era < 10)
342+
rng_inst = (rd_reg32(&priv->ctrl->perfmon.cha_num_ls) &
343+
CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
344+
else
345+
rng_inst = rd_reg32(&priv->ctrl->vreg.rng) & CHA_VER_NUM_MASK;
346+
347+
if (!rng_inst)
340348
return -ENODEV;
341349

342350
dev = caam_jr_alloc();

‎drivers/crypto/caam/ctrl.c

Lines changed: 21 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
* Controller-level driver, kernel property detection, initialization
44
*
55
* Copyright 2008-2012 Freescale Semiconductor, Inc.
6+
* Copyright 2018 NXP
67
*/
78

89
#include <linux/device.h>
@@ -106,7 +107,7 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
106107
struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
107108
struct caam_deco __iomem *deco = ctrlpriv->deco;
108109
unsigned int timeout = 100000;
109-
u32 deco_dbg_reg, flags;
110+
u32 deco_dbg_reg, deco_state, flags;
110111
int i;
111112

112113

@@ -149,13 +150,22 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
149150
timeout = 10000000;
150151
do {
151152
deco_dbg_reg = rd_reg32(&deco->desc_dbg);
153+
154+
if (ctrlpriv->era < 10)
155+
deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
156+
DESC_DBG_DECO_STAT_SHIFT;
157+
else
158+
deco_state = (rd_reg32(&deco->dbg_exec) &
159+
DESC_DER_DECO_STAT_MASK) >>
160+
DESC_DER_DECO_STAT_SHIFT;
161+
152162
/*
153163
* If an error occured in the descriptor, then
154164
* the DECO status field will be set to 0x0D
155165
*/
156-
if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
157-
DESC_DBG_DECO_STAT_HOST_ERR)
166+
if (deco_state == DECO_STAT_HOST_ERR)
158167
break;
168+
159169
cpu_relax();
160170
} while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
161171

@@ -491,7 +501,7 @@ static int caam_probe(struct platform_device *pdev)
491501
struct caam_perfmon *perfmon;
492502
#endif
493503
u32 scfgr, comp_params;
494-
u32 cha_vid_ls;
504+
u8 rng_vid;
495505
int pg_size;
496506
int BLOCK_OFFSET = 0;
497507

@@ -733,15 +743,19 @@ static int caam_probe(struct platform_device *pdev)
733743
goto caam_remove;
734744
}
735745

736-
cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
746+
if (ctrlpriv->era < 10)
747+
rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) &
748+
CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
749+
else
750+
rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
751+
CHA_VER_VID_SHIFT;
737752

738753
/*
739754
* If SEC has RNG version >= 4 and RNG state handle has not been
740755
* already instantiated, do RNG instantiation
741756
* In case of SoCs with Management Complex, RNG is managed by MC f/w.
742757
*/
743-
if (!ctrlpriv->mc_en &&
744-
(cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
758+
if (!ctrlpriv->mc_en && rng_vid >= 4) {
745759
ctrlpriv->rng4_sh_init =
746760
rd_reg32(&ctrl->r4tst[0].rdsta);
747761
/*

‎drivers/crypto/caam/desc.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
* Definitions to support CAAM descriptor instruction generation
55
*
66
* Copyright 2008-2011 Freescale Semiconductor, Inc.
7+
* Copyright 2018 NXP
78
*/
89

910
#ifndef DESC_H
@@ -1133,6 +1134,12 @@
11331134
#define OP_ALG_TYPE_CLASS1 (2 << OP_ALG_TYPE_SHIFT)
11341135
#define OP_ALG_TYPE_CLASS2 (4 << OP_ALG_TYPE_SHIFT)
11351136

1137+
/* version register fields */
1138+
#define OP_VER_CCHA_NUM 0x000000ff /* Number CCHAs instantiated */
1139+
#define OP_VER_CCHA_MISC 0x0000ff00 /* CCHA Miscellaneous Information */
1140+
#define OP_VER_CCHA_REV 0x00ff0000 /* CCHA Revision Number */
1141+
#define OP_VER_CCHA_VID 0xff000000 /* CCHA Version ID */
1142+
11361143
#define OP_ALG_ALGSEL_SHIFT 16
11371144
#define OP_ALG_ALGSEL_MASK (0xff << OP_ALG_ALGSEL_SHIFT)
11381145
#define OP_ALG_ALGSEL_SUBMASK (0x0f << OP_ALG_ALGSEL_SHIFT)

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