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torvaldstorvalds
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Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 apic changes from Ingo Molnar: "The main changes in this cycle were: - Numachip updates: new hardware support, fixes and cleanups. (Daniel J Blueman) - misc smaller cleanups and fixlets" * 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/io_apic: Make eoi_ioapic_pin() static x86/irq: Drop unlikely before IS_ERR_OR_NULL x86/x2apic: Make stub functions available even if !CONFIG_X86_LOCAL_APIC x86/apic: Deinline various functions x86/numachip: Fix timer build conflict x86/numachip: Introduce Numachip2 timer mechanisms x86/numachip: Add Numachip IPI optimisations x86/numachip: Add Numachip2 APIC support x86/numachip: Cleanup Numachip support
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9 files changed

+360
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lines changed

‎arch/x86/include/asm/apic.h

Lines changed: 55 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,59 @@ static inline bool apic_is_x2apic_enabled(void)
115115
return msr & X2APIC_ENABLE;
116116
}
117117

118+
extern void enable_IR_x2apic(void);
119+
120+
extern int get_physical_broadcast(void);
121+
122+
extern int lapic_get_maxlvt(void);
123+
extern void clear_local_APIC(void);
124+
extern void disconnect_bsp_APIC(int virt_wire_setup);
125+
extern void disable_local_APIC(void);
126+
extern void lapic_shutdown(void);
127+
extern void sync_Arb_IDs(void);
128+
extern void init_bsp_APIC(void);
129+
extern void setup_local_APIC(void);
130+
extern void init_apic_mappings(void);
131+
void register_lapic_address(unsigned long address);
132+
extern void setup_boot_APIC_clock(void);
133+
extern void setup_secondary_APIC_clock(void);
134+
extern int APIC_init_uniprocessor(void);
135+
136+
#ifdef CONFIG_X86_64
137+
static inline int apic_force_enable(unsigned long addr)
138+
{
139+
return -1;
140+
}
141+
#else
142+
extern int apic_force_enable(unsigned long addr);
143+
#endif
144+
145+
extern int apic_bsp_setup(bool upmode);
146+
extern void apic_ap_setup(void);
147+
148+
/*
149+
* On 32bit this is mach-xxx local
150+
*/
151+
#ifdef CONFIG_X86_64
152+
extern int apic_is_clustered_box(void);
153+
#else
154+
static inline int apic_is_clustered_box(void)
155+
{
156+
return 0;
157+
}
158+
#endif
159+
160+
extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
161+
162+
#else /* !CONFIG_X86_LOCAL_APIC */
163+
static inline void lapic_shutdown(void) { }
164+
#define local_apic_timer_c2_ok 1
165+
static inline void init_apic_mappings(void) { }
166+
static inline void disable_local_APIC(void) { }
167+
# define setup_boot_APIC_clock x86_init_noop
168+
# define setup_secondary_APIC_clock x86_init_noop
169+
#endif /* !CONFIG_X86_LOCAL_APIC */
170+
118171
#ifdef CONFIG_X86_X2APIC
119172
/*
120173
* Make previous memory operations globally visible before
@@ -186,67 +239,14 @@ static inline int x2apic_enabled(void)
186239
}
187240

188241
#define x2apic_supported() (cpu_has_x2apic)
189-
#else
242+
#else /* !CONFIG_X86_X2APIC */
190243
static inline void check_x2apic(void) { }
191244
static inline void x2apic_setup(void) { }
192245
static inline int x2apic_enabled(void) { return 0; }
193246

194247
#define x2apic_mode (0)
195248
#define x2apic_supported() (0)
196-
#endif
197-
198-
extern void enable_IR_x2apic(void);
199-
200-
extern int get_physical_broadcast(void);
201-
202-
extern int lapic_get_maxlvt(void);
203-
extern void clear_local_APIC(void);
204-
extern void disconnect_bsp_APIC(int virt_wire_setup);
205-
extern void disable_local_APIC(void);
206-
extern void lapic_shutdown(void);
207-
extern void sync_Arb_IDs(void);
208-
extern void init_bsp_APIC(void);
209-
extern void setup_local_APIC(void);
210-
extern void init_apic_mappings(void);
211-
void register_lapic_address(unsigned long address);
212-
extern void setup_boot_APIC_clock(void);
213-
extern void setup_secondary_APIC_clock(void);
214-
extern int APIC_init_uniprocessor(void);
215-
216-
#ifdef CONFIG_X86_64
217-
static inline int apic_force_enable(unsigned long addr)
218-
{
219-
return -1;
220-
}
221-
#else
222-
extern int apic_force_enable(unsigned long addr);
223-
#endif
224-
225-
extern int apic_bsp_setup(bool upmode);
226-
extern void apic_ap_setup(void);
227-
228-
/*
229-
* On 32bit this is mach-xxx local
230-
*/
231-
#ifdef CONFIG_X86_64
232-
extern int apic_is_clustered_box(void);
233-
#else
234-
static inline int apic_is_clustered_box(void)
235-
{
236-
return 0;
237-
}
238-
#endif
239-
240-
extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
241-
242-
#else /* !CONFIG_X86_LOCAL_APIC */
243-
static inline void lapic_shutdown(void) { }
244-
#define local_apic_timer_c2_ok 1
245-
static inline void init_apic_mappings(void) { }
246-
static inline void disable_local_APIC(void) { }
247-
# define setup_boot_APIC_clock x86_init_noop
248-
# define setup_secondary_APIC_clock x86_init_noop
249-
#endif /* !CONFIG_X86_LOCAL_APIC */
249+
#endif /* !CONFIG_X86_X2APIC */
250250

251251
#ifdef CONFIG_X86_64
252252
#define SET_APIC_ID(x) (apic->set_apic_id(x))

‎arch/x86/include/asm/numachip/numachip.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#ifndef _ASM_X86_NUMACHIP_NUMACHIP_H
1515
#define _ASM_X86_NUMACHIP_NUMACHIP_H
1616

17+
extern u8 numachip_system;
1718
extern int __init pci_numachip_init(void);
1819

1920
#endif /* _ASM_X86_NUMACHIP_NUMACHIP_H */

‎arch/x86/include/asm/numachip/numachip_csr.h

Lines changed: 42 additions & 111 deletions
Original file line numberDiff line numberDiff line change
@@ -14,24 +14,17 @@
1414
#ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
1515
#define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
1616

17-
#include <linux/numa.h>
18-
#include <linux/percpu.h>
17+
#include <linux/smp.h>
1918
#include <linux/io.h>
20-
#include <linux/swab.h>
21-
#include <asm/types.h>
22-
#include <asm/processor.h>
2319

2420
#define CSR_NODE_SHIFT 16
2521
#define CSR_NODE_BITS(p) (((unsigned long)(p)) << CSR_NODE_SHIFT)
2622
#define CSR_NODE_MASK 0x0fff /* 4K nodes */
2723

2824
/* 32K CSR space, b15 indicates geo/non-geo */
2925
#define CSR_OFFSET_MASK 0x7fffUL
30-
31-
/* Global CSR space covers all 4K possible nodes with 64K CSR space per node */
32-
#define NUMACHIP_GCSR_BASE 0x3fff00000000ULL
33-
#define NUMACHIP_GCSR_LIM 0x3fff0fffffffULL
34-
#define NUMACHIP_GCSR_SIZE (NUMACHIP_GCSR_LIM - NUMACHIP_GCSR_BASE + 1)
26+
#define CSR_G0_NODE_IDS (0x008 + (0 << 12))
27+
#define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))
3528

3629
/*
3730
* Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
@@ -41,127 +34,65 @@
4134
#define NUMACHIP_LCSR_BASE 0x3ffffe000000ULL
4235
#define NUMACHIP_LCSR_LIM 0x3fffffffffffULL
4336
#define NUMACHIP_LCSR_SIZE (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
44-
45-
static inline void *gcsr_address(int node, unsigned long offset)
46-
{
47-
return __va(NUMACHIP_GCSR_BASE | (1UL << 15) |
48-
CSR_NODE_BITS(node & CSR_NODE_MASK) | (offset & CSR_OFFSET_MASK));
49-
}
37+
#define NUMACHIP_LAPIC_BITS 8
5038

5139
static inline void *lcsr_address(unsigned long offset)
5240
{
5341
return __va(NUMACHIP_LCSR_BASE | (1UL << 15) |
5442
CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK));
5543
}
5644

57-
static inline unsigned int read_gcsr(int node, unsigned long offset)
45+
static inline unsigned int read_lcsr(unsigned long offset)
5846
{
59-
return swab32(readl(gcsr_address(node, offset)));
47+
return swab32(readl(lcsr_address(offset)));
6048
}
6149

62-
static inline void write_gcsr(int node, unsigned long offset, unsigned int val)
50+
static inline void write_lcsr(unsigned long offset, unsigned int val)
6351
{
64-
writel(swab32(val), gcsr_address(node, offset));
52+
writel(swab32(val), lcsr_address(offset));
6553
}
6654

67-
static inline unsigned int read_lcsr(unsigned long offset)
55+
/*
56+
* On NumaChip2, local CSR space is 16MB and starts at fixed offset below 4G
57+
*/
58+
59+
#define NUMACHIP2_LCSR_BASE 0xf0000000UL
60+
#define NUMACHIP2_LCSR_SIZE 0x1000000UL
61+
#define NUMACHIP2_APIC_ICR 0x100000
62+
#define NUMACHIP2_TIMER_DEADLINE 0x200000
63+
#define NUMACHIP2_TIMER_INT 0x200008
64+
#define NUMACHIP2_TIMER_NOW 0x200018
65+
#define NUMACHIP2_TIMER_RESET 0x200020
66+
67+
static inline void __iomem *numachip2_lcsr_address(unsigned long offset)
6868
{
69-
return swab32(readl(lcsr_address(offset)));
69+
return (void __iomem *)__va(NUMACHIP2_LCSR_BASE |
70+
(offset & (NUMACHIP2_LCSR_SIZE - 1)));
7071
}
7172

72-
static inline void write_lcsr(unsigned long offset, unsigned int val)
73+
static inline u32 numachip2_read32_lcsr(unsigned long offset)
7374
{
74-
writel(swab32(val), lcsr_address(offset));
75+
return readl(numachip2_lcsr_address(offset));
7576
}
7677

77-
/* ========================================================================= */
78-
/* CSR_G0_STATE_CLEAR */
79-
/* ========================================================================= */
80-
81-
#define CSR_G0_STATE_CLEAR (0x000 + (0 << 12))
82-
union numachip_csr_g0_state_clear {
83-
unsigned int v;
84-
struct numachip_csr_g0_state_clear_s {
85-
unsigned int _state:2;
86-
unsigned int _rsvd_2_6:5;
87-
unsigned int _lost:1;
88-
unsigned int _rsvd_8_31:24;
89-
} s;
90-
};
91-
92-
/* ========================================================================= */
93-
/* CSR_G0_NODE_IDS */
94-
/* ========================================================================= */
78+
static inline u64 numachip2_read64_lcsr(unsigned long offset)
79+
{
80+
return readq(numachip2_lcsr_address(offset));
81+
}
9582

96-
#define CSR_G0_NODE_IDS (0x008 + (0 << 12))
97-
union numachip_csr_g0_node_ids {
98-
unsigned int v;
99-
struct numachip_csr_g0_node_ids_s {
100-
unsigned int _initialid:16;
101-
unsigned int _nodeid:12;
102-
unsigned int _rsvd_28_31:4;
103-
} s;
104-
};
105-
106-
/* ========================================================================= */
107-
/* CSR_G3_EXT_IRQ_GEN */
108-
/* ========================================================================= */
83+
static inline void numachip2_write32_lcsr(unsigned long offset, u32 val)
84+
{
85+
writel(val, numachip2_lcsr_address(offset));
86+
}
10987

110-
#define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))
111-
union numachip_csr_g3_ext_irq_gen {
112-
unsigned int v;
113-
struct numachip_csr_g3_ext_irq_gen_s {
114-
unsigned int _vector:8;
115-
unsigned int _msgtype:3;
116-
unsigned int _index:5;
117-
unsigned int _destination_apic_id:16;
118-
} s;
119-
};
120-
121-
/* ========================================================================= */
122-
/* CSR_G3_EXT_IRQ_STATUS */
123-
/* ========================================================================= */
124-
125-
#define CSR_G3_EXT_IRQ_STATUS (0x034 + (3 << 12))
126-
union numachip_csr_g3_ext_irq_status {
127-
unsigned int v;
128-
struct numachip_csr_g3_ext_irq_status_s {
129-
unsigned int _result:32;
130-
} s;
131-
};
132-
133-
/* ========================================================================= */
134-
/* CSR_G3_EXT_IRQ_DEST */
135-
/* ========================================================================= */
136-
137-
#define CSR_G3_EXT_IRQ_DEST (0x038 + (3 << 12))
138-
union numachip_csr_g3_ext_irq_dest {
139-
unsigned int v;
140-
struct numachip_csr_g3_ext_irq_dest_s {
141-
unsigned int _irq:8;
142-
unsigned int _rsvd_8_31:24;
143-
} s;
144-
};
145-
146-
/* ========================================================================= */
147-
/* CSR_G3_NC_ATT_MAP_SELECT */
148-
/* ========================================================================= */
149-
150-
#define CSR_G3_NC_ATT_MAP_SELECT (0x7fc + (3 << 12))
151-
union numachip_csr_g3_nc_att_map_select {
152-
unsigned int v;
153-
struct numachip_csr_g3_nc_att_map_select_s {
154-
unsigned int _upper_address_bits:4;
155-
unsigned int _select_ram:4;
156-
unsigned int _rsvd_8_31:24;
157-
} s;
158-
};
159-
160-
/* ========================================================================= */
161-
/* CSR_G3_NC_ATT_MAP_SELECT_0-255 */
162-
/* ========================================================================= */
163-
164-
#define CSR_G3_NC_ATT_MAP_SELECT_0 (0x800 + (3 << 12))
88+
static inline void numachip2_write64_lcsr(unsigned long offset, u64 val)
89+
{
90+
writeq(val, numachip2_lcsr_address(offset));
91+
}
16592

166-
#endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */
93+
static inline unsigned int numachip2_timer(void)
94+
{
95+
return (smp_processor_id() % 48) << 6;
96+
}
16797

98+
#endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */

‎arch/x86/kernel/apic/apic.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1431,7 +1431,7 @@ enum {
14311431
};
14321432
static int x2apic_state;
14331433

1434-
static inline void __x2apic_disable(void)
1434+
static void __x2apic_disable(void)
14351435
{
14361436
u64 msr;
14371437

@@ -1447,7 +1447,7 @@ static inline void __x2apic_disable(void)
14471447
printk_once(KERN_INFO "x2apic disabled\n");
14481448
}
14491449

1450-
static inline void __x2apic_enable(void)
1450+
static void __x2apic_enable(void)
14511451
{
14521452
u64 msr;
14531453

@@ -1807,7 +1807,7 @@ int apic_version[MAX_LOCAL_APIC];
18071807
/*
18081808
* This interrupt should _never_ happen with our APIC/SMP architecture
18091809
*/
1810-
static inline void __smp_spurious_interrupt(u8 vector)
1810+
static void __smp_spurious_interrupt(u8 vector)
18111811
{
18121812
u32 v;
18131813

@@ -1848,7 +1848,7 @@ __visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
18481848
/*
18491849
* This interrupt should never happen with our APIC/SMP architecture
18501850
*/
1851-
static inline void __smp_error_interrupt(struct pt_regs *regs)
1851+
static void __smp_error_interrupt(struct pt_regs *regs)
18521852
{
18531853
u32 v;
18541854
u32 i = 0;

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