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Merge tag 'pci-v4.5-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas: "PCI changes for the v4.5 merge window: Enumeration: - Simplify config space size computation (Bjorn Helgaas) - Avoid iterating through ROM outside the resource window (Edward O'Callaghan) - Support PCIe devices with short cfg_size (Jason S. McMullan) - Add Netronome vendor and device IDs (Jason S. McMullan) - Limit config space size for Netronome NFP6000 family (Jason S. McMullan) - Add Netronome NFP4000 PF device ID (Simon Horman) - Limit config space size for Netronome NFP4000 (Simon Horman) - Print warnings for all invalid expansion ROM headers (Vladis Dronov) Resource management: - Fix minimum allocation address overwrite (Christoph Biedl) PCI device hotplug: - acpiphp_ibm: Fix null dereferences on null ibm_slot (Colin Ian King) - pciehp: Always protect pciehp_disable_slot() with hotplug mutex (Guenter Roeck) - shpchp: Constify hpc_ops structure (Julia Lawall) - ibmphp: Remove unneeded NULL test (Julia Lawall) Power management: - Make ASPM sysfs link_state_store() consistent with link_state_show() (Andy Lutomirski) Virtualization - Add function 1 DMA alias quirk for Lite-On/Plextor M6e/Marvell 88SS9183 (Tim Sander) MSI: - Remove empty pci_msi_init_pci_dev() (Bjorn Helgaas) - Mark PCIe/PCI (MSI) IRQ cascade handlers as IRQF_NO_THREAD (Grygorii Strashko) - Initialize MSI capability for all architectures (Guilherme G. Piccoli) - Relax msi_domain_alloc() to support parentless MSI irqdomains (Liu Jiang) ARM Versatile host bridge driver: - Remove unused pci_sys_data structures (Lorenzo Pieralisi) Broadcom iProc host bridge driver: - Hide CONFIG_PCIE_IPROC (Arnd Bergmann) - Do not use 0x in front of %pap (Dmitry V. Krivenok) - Update iProc PCIe device tree binding (Ray Jui) - Add PAXC interface support (Ray Jui) - Add iProc PCIe MSI device tree binding (Ray Jui) - Add iProc PCIe MSI support (Ray Jui) Freescale i.MX6 host bridge driver: - Use gpio_set_value_cansleep() (Fabio Estevam) - Add support for active-low reset GPIO (Petr Štetiar) HiSilicon host bridge driver: - Add support for HiSilicon Hip06 PCIe host controllers (Gabriele Paoloni) Intel VMD host bridge driver: - Export irq_domain_set_info() for module use (Keith Busch) - x86/PCI: Allow DMA ops specific to a PCI domain (Keith Busch) - Use 32 bit PCI domain numbers (Keith Busch) - Add driver for Intel Volume Management Device (VMD) (Keith Busch) Qualcomm host bridge driver: - Document PCIe devicetree bindings (Stanimir Varbanov) - Add Qualcomm PCIe controller driver (Stanimir Varbanov) - dts: apq8064: add PCIe devicetree node (Stanimir Varbanov) - dts: ifc6410: enable PCIe DT node for this board (Stanimir Varbanov) Renesas R-Car host bridge driver: - Add support for R-Car H3 to pcie-rcar (Harunobu Kurokawa) - Allow DT to override default window settings (Phil Edworthy) - Convert to DT resource parsing API (Phil Edworthy) - Revert "PCI: rcar: Build pcie-rcar.c only on ARM" (Phil Edworthy) - Remove unused pci_sys_data struct from pcie-rcar (Phil Edworthy) - Add runtime PM support to pcie-rcar (Phil Edworthy) - Add Gen2 PHY setup to pcie-rcar (Phil Edworthy) - Add gen2 fallback compatibility string for pci-rcar-gen2 (Simon Horman) - Add gen2 fallback compatibility string for pcie-rcar (Simon Horman) Synopsys DesignWare host bridge driver: - Simplify control flow (Bjorn Helgaas) - Make config accessor override checking symmetric (Bjorn Helgaas) - Ensure ATU is enabled before IO/conf space accesses (Stanimir Varbanov) Miscellaneous: - Add of_pci_get_host_bridge_resources() stub (Arnd Bergmann) - Check for PCI_HEADER_TYPE_BRIDGE equality, not bitmask (Bjorn Helgaas) - Fix all whitespace issues (Bogicevic Sasa) - x86/PCI: Simplify pci_bios_{read,write} (Geliang Tang) - Use to_pci_dev() instead of open-coding it (Geliang Tang) - Use kobj_to_dev() instead of open-coding it (Geliang Tang) - Use list_for_each_entry() to simplify code (Geliang Tang) - Fix typos in <linux/msi.h> (Thomas Petazzoni) - x86/PCI: Clarify AMD Fam10h config access restrictions comment (Tomasz Nowicki)" * tag 'pci-v4.5-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (58 commits) PCI: Add function 1 DMA alias quirk for Lite-On/Plextor M6e/Marvell 88SS9183 PCI: Limit config space size for Netronome NFP4000 PCI: Add Netronome NFP4000 PF device ID x86/PCI: Add driver for Intel Volume Management Device (VMD) PCI/AER: Use 32 bit PCI domain numbers x86/PCI: Allow DMA ops specific to a PCI domain irqdomain: Export irq_domain_set_info() for module use PCI: host: Add of_pci_get_host_bridge_resources() stub genirq/MSI: Relax msi_domain_alloc() to support parentless MSI irqdomains PCI: rcar: Add Gen2 PHY setup to pcie-rcar PCI: rcar: Add runtime PM support to pcie-rcar PCI: designware: Make config accessor override checking symmetric PCI: ibmphp: Remove unneeded NULL test ARM: dts: ifc6410: enable PCIe DT node for this board ARM: dts: apq8064: add PCIe devicetree node PCI: hotplug: Use list_for_each_entry() to simplify code PCI: rcar: Remove unused pci_sys_data struct from pcie-rcar PCI: hisi: Add support for HiSilicon Hip06 PCIe host controllers PCI: Avoid iterating through memory outside the resource window PCI: acpiphp_ibm: Fix null dereferences on null ibm_slot ...
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‎Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,10 @@
11
* Broadcom iProc PCIe controller with the platform bus interface
22

33
Required properties:
4-
- compatible: Must be "brcm,iproc-pcie"
4+
- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc"
5+
for PAXC. PAXB-based root complex is used for external endpoint devices.
6+
PAXC-based root complex is connected to emulated endpoint devices
7+
internal to the ASIC
58
- reg: base address and length of the PCIe controller I/O register space
69
- #interrupt-cells: set to <1>
710
- interrupt-map-mask and interrupt-map, standard PCI properties to define the
@@ -32,6 +35,28 @@ Optional:
3235
- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
3336
increase the outbound window size
3437

38+
MSI support (optional):
39+
40+
For older platforms without MSI integrated in the GIC, iProc PCIe core provides
41+
an event queue based MSI support. The iProc MSI uses host memories to store
42+
MSI posted writes in the event queues
43+
44+
- msi-parent: Link to the device node of the MSI controller. On newer iProc
45+
platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc
46+
platforms without MSI support in its interrupt controller, one may use the
47+
event queue based MSI support integrated within the iProc PCIe core.
48+
49+
When the iProc event queue based MSI is used, one needs to define the
50+
following properties in the MSI device node:
51+
- compatible: Must be "brcm,iproc-msi"
52+
- msi-controller: claims itself as an MSI controller
53+
- interrupt-parent: Link to its parent interrupt device
54+
- interrupts: List of interrupt IDs from its parent interrupt device
55+
56+
Optional properties:
57+
- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
58+
require the interrupt enable registers to be set explicitly to enable MSI
59+
3560
Example:
3661
pcie0: pcie@18012000 {
3762
compatible = "brcm,iproc-pcie";
@@ -58,6 +83,19 @@ Example:
5883
brcm,pcie-ob-oarr-size;
5984
brcm,pcie-ob-axi-offset = <0x00000000>;
6085
brcm,pcie-ob-window-size = <256>;
86+
87+
msi-parent = <&msi0>;
88+
89+
/* iProc event queue based MSI */
90+
msi0: msi@18012000 {
91+
compatible = "brcm,iproc-msi";
92+
msi-controller;
93+
interrupt-parent = <&gic>;
94+
interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
95+
<GIC_SPI 97 IRQ_TYPE_NONE>,
96+
<GIC_SPI 98 IRQ_TYPE_NONE>,
97+
<GIC_SPI 99 IRQ_TYPE_NONE>,
98+
};
6199
};
62100

63101
pcie1: pcie@18013000 {

‎Documentation/devicetree/bindings/pci/hisilicon-pcie.txt

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
HiSilicon PCIe host bridge DT description
1+
HiSilicon Hip05 and Hip06 PCIe host bridge DT description
22

33
HiSilicon PCIe host controller is based on Designware PCI core.
44
It shares common functions with PCIe Designware core driver and inherits
@@ -7,8 +7,8 @@ Documentation/devicetree/bindings/pci/designware-pci.txt.
77

88
Additional properties are described here:
99

10-
Required properties:
11-
- compatible: Should contain "hisilicon,hip05-pcie".
10+
Required properties
11+
- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
1212
- reg: Should contain rc_dbi, config registers location and length.
1313
- reg-names: Must include the following entries:
1414
"rc_dbi": controller configuration registers;
@@ -20,7 +20,7 @@ Optional properties:
2020
- status: Either "ok" or "disabled".
2121
- dma-coherent: Present if DMA operations are coherent.
2222

23-
Example:
23+
Hip05 Example (note that Hip06 is the same except compatible):
2424
pcie@0xb0080000 {
2525
compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
2626
reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;

‎Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,14 @@ OHCI and EHCI controllers.
88
Required properties:
99
- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
1010
"renesas,pci-r8a7791" for the R8A7791 SoC;
11-
"renesas,pci-r8a7794" for the R8A7794 SoC.
11+
"renesas,pci-r8a7794" for the R8A7794 SoC;
12+
"renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
13+
14+
15+
When compatible with the generic version, nodes must list the
16+
SoC-specific version corresponding to the platform first
17+
followed by the generic version.
18+
1219
- reg: A list of physical regions to access the device: the first is
1320
the operational registers for the OHCI/EHCI controllers and the
1421
second is for the bridge configuration and control registers.
@@ -24,10 +31,15 @@ Required properties:
2431
- interrupt-map-mask: standard property that helps to define the interrupt
2532
mapping.
2633

34+
Optional properties:
35+
- dma-ranges: a single range for the inbound memory region. If not supplied,
36+
defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
37+
allowed combinations of address and size.
38+
2739
Example SoC configuration:
2840

2941
pci0: pci@ee090000 {
30-
compatible = "renesas,pci-r8a7790";
42+
compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
3143
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
3244
reg = <0x0 0xee090000 0x0 0xc00>,
3345
<0x0 0xee080000 0x0 0x1100>;
@@ -38,6 +50,7 @@ Example SoC configuration:
3850
#address-cells = <3>;
3951
#size-cells = <2>;
4052
#interrupt-cells = <1>;
53+
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
4154
interrupt-map-mask = <0xff00 0 0 0x7>;
4255
interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
4356
0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH

‎Documentation/devicetree/bindings/pci/qcom,pcie.txt

Lines changed: 233 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,233 @@
1+
* Qualcomm PCI express root complex
2+
3+
- compatible:
4+
Usage: required
5+
Value type: <stringlist>
6+
Definition: Value should contain
7+
- "qcom,pcie-ipq8064" for ipq8064
8+
- "qcom,pcie-apq8064" for apq8064
9+
- "qcom,pcie-apq8084" for apq8084
10+
11+
- reg:
12+
Usage: required
13+
Value type: <prop-encoded-array>
14+
Definition: Register ranges as listed in the reg-names property
15+
16+
- reg-names:
17+
Usage: required
18+
Value type: <stringlist>
19+
Definition: Must include the following entries
20+
- "parf" Qualcomm specific registers
21+
- "dbi" Designware PCIe registers
22+
- "elbi" External local bus interface registers
23+
- "config" PCIe configuration space
24+
25+
- device_type:
26+
Usage: required
27+
Value type: <string>
28+
Definition: Should be "pci". As specified in designware-pcie.txt
29+
30+
- #address-cells:
31+
Usage: required
32+
Value type: <u32>
33+
Definition: Should be 3. As specified in designware-pcie.txt
34+
35+
- #size-cells:
36+
Usage: required
37+
Value type: <u32>
38+
Definition: Should be 2. As specified in designware-pcie.txt
39+
40+
- ranges:
41+
Usage: required
42+
Value type: <prop-encoded-array>
43+
Definition: As specified in designware-pcie.txt
44+
45+
- interrupts:
46+
Usage: required
47+
Value type: <prop-encoded-array>
48+
Definition: MSI interrupt
49+
50+
- interrupt-names:
51+
Usage: required
52+
Value type: <stringlist>
53+
Definition: Should contain "msi"
54+
55+
- #interrupt-cells:
56+
Usage: required
57+
Value type: <u32>
58+
Definition: Should be 1. As specified in designware-pcie.txt
59+
60+
- interrupt-map-mask:
61+
Usage: required
62+
Value type: <prop-encoded-array>
63+
Definition: As specified in designware-pcie.txt
64+
65+
- interrupt-map:
66+
Usage: required
67+
Value type: <prop-encoded-array>
68+
Definition: As specified in designware-pcie.txt
69+
70+
- clocks:
71+
Usage: required
72+
Value type: <prop-encoded-array>
73+
Definition: List of phandle and clock specifier pairs as listed
74+
in clock-names property
75+
76+
- clock-names:
77+
Usage: required
78+
Value type: <stringlist>
79+
Definition: Should contain the following entries
80+
- "iface" Configuration AHB clock
81+
82+
- clock-names:
83+
Usage: required for ipq/apq8064
84+
Value type: <stringlist>
85+
Definition: Should contain the following entries
86+
- "core" Clocks the pcie hw block
87+
- "phy" Clocks the pcie PHY block
88+
- clock-names:
89+
Usage: required for apq8084
90+
Value type: <stringlist>
91+
Definition: Should contain the following entries
92+
- "aux" Auxiliary (AUX) clock
93+
- "bus_master" Master AXI clock
94+
- "bus_slave" Slave AXI clock
95+
- resets:
96+
Usage: required
97+
Value type: <prop-encoded-array>
98+
Definition: List of phandle and reset specifier pairs as listed
99+
in reset-names property
100+
101+
- reset-names:
102+
Usage: required for ipq/apq8064
103+
Value type: <stringlist>
104+
Definition: Should contain the following entries
105+
- "axi" AXI reset
106+
- "ahb" AHB reset
107+
- "por" POR reset
108+
- "pci" PCI reset
109+
- "phy" PHY reset
110+
111+
- reset-names:
112+
Usage: required for apq8084
113+
Value type: <stringlist>
114+
Definition: Should contain the following entries
115+
- "core" Core reset
116+
117+
- power-domains:
118+
Usage: required for apq8084
119+
Value type: <prop-encoded-array>
120+
Definition: A phandle and power domain specifier pair to the
121+
power domain which is responsible for collapsing
122+
and restoring power to the peripheral
123+
124+
- vdda-supply:
125+
Usage: required
126+
Value type: <phandle>
127+
Definition: A phandle to the core analog power supply
128+
129+
- vdda_phy-supply:
130+
Usage: required for ipq/apq8064
131+
Value type: <phandle>
132+
Definition: A phandle to the analog power supply for PHY
133+
134+
- vdda_refclk-supply:
135+
Usage: required for ipq/apq8064
136+
Value type: <phandle>
137+
Definition: A phandle to the analog power supply for IC which generates
138+
reference clock
139+
140+
- phys:
141+
Usage: required for apq8084
142+
Value type: <phandle>
143+
Definition: List of phandle(s) as listed in phy-names property
144+
145+
- phy-names:
146+
Usage: required for apq8084
147+
Value type: <stringlist>
148+
Definition: Should contain "pciephy"
149+
150+
- <name>-gpios:
151+
Usage: optional
152+
Value type: <prop-encoded-array>
153+
Definition: List of phandle and gpio specifier pairs. Should contain
154+
- "perst-gpios" PCIe endpoint reset signal line
155+
- "wake-gpios" PCIe endpoint wake signal line
156+
157+
* Example for ipq/apq8064
158+
pcie@1b500000 {
159+
compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
160+
reg = <0x1b500000 0x1000
161+
0x1b502000 0x80
162+
0x1b600000 0x100
163+
0x0ff00000 0x100000>;
164+
reg-names = "dbi", "elbi", "parf", "config";
165+
device_type = "pci";
166+
linux,pci-domain = <0>;
167+
bus-range = <0x00 0xff>;
168+
num-lanes = <1>;
169+
#address-cells = <3>;
170+
#size-cells = <2>;
171+
ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
172+
0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
173+
interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
174+
interrupt-names = "msi";
175+
#interrupt-cells = <1>;
176+
interrupt-map-mask = <0 0 0 0x7>;
177+
interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
178+
<0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
179+
<0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
180+
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
181+
clocks = <&gcc PCIE_A_CLK>,
182+
<&gcc PCIE_H_CLK>,
183+
<&gcc PCIE_PHY_CLK>;
184+
clock-names = "core", "iface", "phy";
185+
resets = <&gcc PCIE_ACLK_RESET>,
186+
<&gcc PCIE_HCLK_RESET>,
187+
<&gcc PCIE_POR_RESET>,
188+
<&gcc PCIE_PCI_RESET>,
189+
<&gcc PCIE_PHY_RESET>;
190+
reset-names = "axi", "ahb", "por", "pci", "phy";
191+
pinctrl-0 = <&pcie_pins_default>;
192+
pinctrl-names = "default";
193+
};
194+
195+
* Example for apq8084
196+
pcie0@fc520000 {
197+
compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
198+
reg = <0xfc520000 0x2000>,
199+
<0xff000000 0x1000>,
200+
<0xff001000 0x1000>,
201+
<0xff002000 0x2000>;
202+
reg-names = "parf", "dbi", "elbi", "config";
203+
device_type = "pci";
204+
linux,pci-domain = <0>;
205+
bus-range = <0x00 0xff>;
206+
num-lanes = <1>;
207+
#address-cells = <3>;
208+
#size-cells = <2>;
209+
ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
210+
0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
211+
interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
212+
interrupt-names = "msi";
213+
#interrupt-cells = <1>;
214+
interrupt-map-mask = <0 0 0 0x7>;
215+
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
216+
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
217+
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
218+
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
219+
clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
220+
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
221+
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
222+
<&gcc GCC_PCIE_0_AUX_CLK>;
223+
clock-names = "iface", "master_bus", "slave_bus", "aux";
224+
resets = <&gcc GCC_PCIE_0_BCR>;
225+
reset-names = "core";
226+
power-domains = <&gcc PCIE0_GDSC>;
227+
vdda-supply = <&pma8084_l3>;
228+
phys = <&pciephy0>;
229+
phy-names = "pciephy";
230+
perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
231+
pinctrl-0 = <&pcie0_pins_default>;
232+
pinctrl-names = "default";
233+
};

‎Documentation/devicetree/bindings/pci/rcar-pci.txt

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,16 @@
11
* Renesas RCar PCIe interface
22

33
Required properties:
4-
- compatible: should contain one of the following
5-
"renesas,pcie-r8a7779", "renesas,pcie-r8a7790", "renesas,pcie-r8a7791"
4+
compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
5+
"renesas,pcie-r8a7790" for the R8A7790 SoC;
6+
"renesas,pcie-r8a7791" for the R8A7791 SoC;
7+
"renesas,pcie-r8a7795" for the R8A7795 SoC;
8+
"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
9+
10+
When compatible with the generic version, nodes must list the
11+
SoC-specific version corresponding to the platform first
12+
followed by the generic version.
13+
614
- reg: base address and length of the pcie controller registers.
715
- #address-cells: set to <3>
816
- #size-cells: set to <2>
@@ -25,7 +33,7 @@ Example:
2533
SoC specific DT Entry:
2634

2735
pcie: pcie@fe000000 {
28-
compatible = "renesas,pcie-r8a7791";
36+
compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
2937
reg = <0 0xfe000000 0 0x80000>;
3038
#address-cells = <3>;
3139
#size-cells = <2>;

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