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torvaldstorvalds
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
Pull sparc fixes from David Miller: "Some perf bug fixes from David Ahern, and the fix for that nasty memmove() bug" * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc: sparc64: Fix several bugs in memmove(). sparc: Touch NMI watchdog when walking cpus and calling printk sparc: perf: Add support M7 processor sparc: perf: Make counting mode actually work sparc: perf: Remove redundant perf_pmu_{en|dis}able calls
2 parents bc465aa + 2077cef commit d504961

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7 files changed

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-15
lines changed

7 files changed

+141
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lines changed

‎arch/sparc/include/asm/hypervisor.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2957,6 +2957,17 @@ unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,
29572957
unsigned long reg_val);
29582958
#endif
29592959

2960+
2961+
#define HV_FAST_M7_GET_PERFREG 0x43
2962+
#define HV_FAST_M7_SET_PERFREG 0x44
2963+
2964+
#ifndef __ASSEMBLY__
2965+
unsigned long sun4v_m7_get_perfreg(unsigned long reg_num,
2966+
unsigned long *reg_val);
2967+
unsigned long sun4v_m7_set_perfreg(unsigned long reg_num,
2968+
unsigned long reg_val);
2969+
#endif
2970+
29602971
/* Function numbers for HV_CORE_TRAP. */
29612972
#define HV_CORE_SET_VER 0x00
29622973
#define HV_CORE_PUTCHAR 0x01
@@ -2981,6 +2992,7 @@ unsigned long sun4v_t5_set_perfreg(unsigned long reg_num,
29812992
#define HV_GRP_SDIO 0x0108
29822993
#define HV_GRP_SDIO_ERR 0x0109
29832994
#define HV_GRP_REBOOT_DATA 0x0110
2995+
#define HV_GRP_M7_PERF 0x0114
29842996
#define HV_GRP_NIAG_PERF 0x0200
29852997
#define HV_GRP_FIRE_PERF 0x0201
29862998
#define HV_GRP_N2_CPU 0x0202

‎arch/sparc/kernel/hvapi.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,7 @@ static struct api_info api_table[] = {
4848
{ .group = HV_GRP_VT_CPU, },
4949
{ .group = HV_GRP_T5_CPU, },
5050
{ .group = HV_GRP_DIAG, .flags = FLAG_PRE_API },
51+
{ .group = HV_GRP_M7_PERF, },
5152
};
5253

5354
static DEFINE_SPINLOCK(hvapi_lock);

‎arch/sparc/kernel/hvcalls.S

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -837,3 +837,19 @@ ENTRY(sun4v_t5_set_perfreg)
837837
retl
838838
nop
839839
ENDPROC(sun4v_t5_set_perfreg)
840+
841+
ENTRY(sun4v_m7_get_perfreg)
842+
mov %o1, %o4
843+
mov HV_FAST_M7_GET_PERFREG, %o5
844+
ta HV_FAST_TRAP
845+
stx %o1, [%o4]
846+
retl
847+
nop
848+
ENDPROC(sun4v_m7_get_perfreg)
849+
850+
ENTRY(sun4v_m7_set_perfreg)
851+
mov HV_FAST_M7_SET_PERFREG, %o5
852+
ta HV_FAST_TRAP
853+
retl
854+
nop
855+
ENDPROC(sun4v_m7_set_perfreg)

‎arch/sparc/kernel/pcr.c

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,31 @@ static const struct pcr_ops n5_pcr_ops = {
217217
.pcr_nmi_disable = PCR_N4_PICNPT,
218218
};
219219

220+
static u64 m7_pcr_read(unsigned long reg_num)
221+
{
222+
unsigned long val;
223+
224+
(void) sun4v_m7_get_perfreg(reg_num, &val);
225+
226+
return val;
227+
}
228+
229+
static void m7_pcr_write(unsigned long reg_num, u64 val)
230+
{
231+
(void) sun4v_m7_set_perfreg(reg_num, val);
232+
}
233+
234+
static const struct pcr_ops m7_pcr_ops = {
235+
.read_pcr = m7_pcr_read,
236+
.write_pcr = m7_pcr_write,
237+
.read_pic = n4_pic_read,
238+
.write_pic = n4_pic_write,
239+
.nmi_picl_value = n4_picl_value,
240+
.pcr_nmi_enable = (PCR_N4_PICNPT | PCR_N4_STRACE |
241+
PCR_N4_UTRACE | PCR_N4_TOE |
242+
(26 << PCR_N4_SL_SHIFT)),
243+
.pcr_nmi_disable = PCR_N4_PICNPT,
244+
};
220245

221246
static unsigned long perf_hsvc_group;
222247
static unsigned long perf_hsvc_major;
@@ -248,6 +273,10 @@ static int __init register_perf_hsvc(void)
248273
perf_hsvc_group = HV_GRP_T5_CPU;
249274
break;
250275

276+
case SUN4V_CHIP_SPARC_M7:
277+
perf_hsvc_group = HV_GRP_M7_PERF;
278+
break;
279+
251280
default:
252281
return -ENODEV;
253282
}
@@ -293,6 +322,10 @@ static int __init setup_sun4v_pcr_ops(void)
293322
pcr_ops = &n5_pcr_ops;
294323
break;
295324

325+
case SUN4V_CHIP_SPARC_M7:
326+
pcr_ops = &m7_pcr_ops;
327+
break;
328+
296329
default:
297330
ret = -ENODEV;
298331
break;

‎arch/sparc/kernel/perf_event.c

Lines changed: 43 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -792,6 +792,42 @@ static const struct sparc_pmu niagara4_pmu = {
792792
.num_pic_regs = 4,
793793
};
794794

795+
static void sparc_m7_write_pmc(int idx, u64 val)
796+
{
797+
u64 pcr;
798+
799+
pcr = pcr_ops->read_pcr(idx);
800+
/* ensure ov and ntc are reset */
801+
pcr &= ~(PCR_N4_OV | PCR_N4_NTC);
802+
803+
pcr_ops->write_pic(idx, val & 0xffffffff);
804+
805+
pcr_ops->write_pcr(idx, pcr);
806+
}
807+
808+
static const struct sparc_pmu sparc_m7_pmu = {
809+
.event_map = niagara4_event_map,
810+
.cache_map = &niagara4_cache_map,
811+
.max_events = ARRAY_SIZE(niagara4_perfmon_event_map),
812+
.read_pmc = sparc_vt_read_pmc,
813+
.write_pmc = sparc_m7_write_pmc,
814+
.upper_shift = 5,
815+
.lower_shift = 5,
816+
.event_mask = 0x7ff,
817+
.user_bit = PCR_N4_UTRACE,
818+
.priv_bit = PCR_N4_STRACE,
819+
820+
/* We explicitly don't support hypervisor tracing. */
821+
.hv_bit = 0,
822+
823+
.irq_bit = PCR_N4_TOE,
824+
.upper_nop = 0,
825+
.lower_nop = 0,
826+
.flags = 0,
827+
.max_hw_events = 4,
828+
.num_pcrs = 4,
829+
.num_pic_regs = 4,
830+
};
795831
static const struct sparc_pmu *sparc_pmu __read_mostly;
796832

797833
static u64 event_encoding(u64 event_id, int idx)
@@ -960,6 +996,8 @@ static void calculate_single_pcr(struct cpu_hw_events *cpuc)
960996
cpuc->pcr[0] |= cpuc->event[0]->hw.config_base;
961997
}
962998

999+
static void sparc_pmu_start(struct perf_event *event, int flags);
1000+
9631001
/* On this PMU each PIC has it's own PCR control register. */
9641002
static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc)
9651003
{
@@ -972,20 +1010,13 @@ static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc)
9721010
struct perf_event *cp = cpuc->event[i];
9731011
struct hw_perf_event *hwc = &cp->hw;
9741012
int idx = hwc->idx;
975-
u64 enc;
9761013

9771014
if (cpuc->current_idx[i] != PIC_NO_INDEX)
9781015
continue;
9791016

980-
sparc_perf_event_set_period(cp, hwc, idx);
9811017
cpuc->current_idx[i] = idx;
9821018

983-
enc = perf_event_get_enc(cpuc->events[i]);
984-
cpuc->pcr[idx] &= ~mask_for_index(idx);
985-
if (hwc->state & PERF_HES_STOPPED)
986-
cpuc->pcr[idx] |= nop_for_index(idx);
987-
else
988-
cpuc->pcr[idx] |= event_encoding(enc, idx);
1019+
sparc_pmu_start(cp, PERF_EF_RELOAD);
9891020
}
9901021
out:
9911022
for (i = 0; i < cpuc->n_events; i++) {
@@ -1101,7 +1132,6 @@ static void sparc_pmu_del(struct perf_event *event, int _flags)
11011132
int i;
11021133

11031134
local_irq_save(flags);
1104-
perf_pmu_disable(event->pmu);
11051135

11061136
for (i = 0; i < cpuc->n_events; i++) {
11071137
if (event == cpuc->event[i]) {
@@ -1127,7 +1157,6 @@ static void sparc_pmu_del(struct perf_event *event, int _flags)
11271157
}
11281158
}
11291159

1130-
perf_pmu_enable(event->pmu);
11311160
local_irq_restore(flags);
11321161
}
11331162

@@ -1361,7 +1390,6 @@ static int sparc_pmu_add(struct perf_event *event, int ef_flags)
13611390
unsigned long flags;
13621391

13631392
local_irq_save(flags);
1364-
perf_pmu_disable(event->pmu);
13651393

13661394
n0 = cpuc->n_events;
13671395
if (n0 >= sparc_pmu->max_hw_events)
@@ -1394,7 +1422,6 @@ static int sparc_pmu_add(struct perf_event *event, int ef_flags)
13941422

13951423
ret = 0;
13961424
out:
1397-
perf_pmu_enable(event->pmu);
13981425
local_irq_restore(flags);
13991426
return ret;
14001427
}
@@ -1667,6 +1694,10 @@ static bool __init supported_pmu(void)
16671694
sparc_pmu = &niagara4_pmu;
16681695
return true;
16691696
}
1697+
if (!strcmp(sparc_pmu_type, "sparc-m7")) {
1698+
sparc_pmu = &sparc_m7_pmu;
1699+
return true;
1700+
}
16701701
return false;
16711702
}
16721703

‎arch/sparc/kernel/process_64.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -287,6 +287,8 @@ void arch_trigger_all_cpu_backtrace(bool include_self)
287287
printk(" TPC[%lx] O7[%lx] I7[%lx] RPC[%lx]\n",
288288
gp->tpc, gp->o7, gp->i7, gp->rpc);
289289
}
290+
291+
touch_nmi_watchdog();
290292
}
291293

292294
memset(global_cpu_snapshot, 0, sizeof(global_cpu_snapshot));
@@ -362,6 +364,8 @@ static void pmu_snapshot_all_cpus(void)
362364
(cpu == this_cpu ? '*' : ' '), cpu,
363365
pp->pcr[0], pp->pcr[1], pp->pcr[2], pp->pcr[3],
364366
pp->pic[0], pp->pic[1], pp->pic[2], pp->pic[3]);
367+
368+
touch_nmi_watchdog();
365369
}
366370

367371
memset(global_cpu_snapshot, 0, sizeof(global_cpu_snapshot));

‎arch/sparc/lib/memmove.S

Lines changed: 32 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,11 @@
88

99
.text
1010
ENTRY(memmove) /* o0=dst o1=src o2=len */
11-
mov %o0, %g1
11+
brz,pn %o2, 99f
12+
mov %o0, %g1
13+
1214
cmp %o0, %o1
13-
bleu,pt %xcc, memcpy
15+
bleu,pt %xcc, 2f
1416
add %o1, %o2, %g7
1517
cmp %g7, %o0
1618
bleu,pt %xcc, memcpy
@@ -24,7 +26,34 @@ ENTRY(memmove) /* o0=dst o1=src o2=len */
2426
stb %g7, [%o0]
2527
bne,pt %icc, 1b
2628
sub %o0, 1, %o0
27-
29+
99:
2830
retl
2931
mov %g1, %o0
32+
33+
/* We can't just call memcpy for these memmove cases. On some
34+
* chips the memcpy uses cache initializing stores and when dst
35+
* and src are close enough, those can clobber the source data
36+
* before we've loaded it in.
37+
*/
38+
2: or %o0, %o1, %g7
39+
or %o2, %g7, %g7
40+
andcc %g7, 0x7, %g0
41+
bne,pn %xcc, 4f
42+
nop
43+
44+
3: ldx [%o1], %g7
45+
add %o1, 8, %o1
46+
subcc %o2, 8, %o2
47+
add %o0, 8, %o0
48+
bne,pt %icc, 3b
49+
stx %g7, [%o0 - 0x8]
50+
ba,a,pt %xcc, 99b
51+
52+
4: ldub [%o1], %g7
53+
add %o1, 1, %o1
54+
subcc %o2, 1, %o2
55+
add %o0, 1, %o0
56+
bne,pt %icc, 4b
57+
stb %g7, [%o0 - 0x1]
58+
ba,a,pt %xcc, 99b
3059
ENDPROC(memmove)

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