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| 1 | +.\" This page Copyright (C) 2010 Len Brown <len.brown@intel.com> |
| 2 | +.\" Distributed under the GPL, Copyleft 1994. |
| 3 | +.TH X86_ENERGY_PERF_POLICY 8 |
| 4 | +.SH NAME |
| 5 | +x86_energy_perf_policy \- read or write MSR_IA32_ENERGY_PERF_BIAS |
| 6 | +.SH SYNOPSIS |
| 7 | +.ft B |
| 8 | +.B x86_energy_perf_policy |
| 9 | +.RB [ "\-c cpu" ] |
| 10 | +.RB [ "\-v" ] |
| 11 | +.RB "\-r" |
| 12 | +.br |
| 13 | +.B x86_energy_perf_policy |
| 14 | +.RB [ "\-c cpu" ] |
| 15 | +.RB [ "\-v" ] |
| 16 | +.RB 'performance' |
| 17 | +.br |
| 18 | +.B x86_energy_perf_policy |
| 19 | +.RB [ "\-c cpu" ] |
| 20 | +.RB [ "\-v" ] |
| 21 | +.RB 'normal' |
| 22 | +.br |
| 23 | +.B x86_energy_perf_policy |
| 24 | +.RB [ "\-c cpu" ] |
| 25 | +.RB [ "\-v" ] |
| 26 | +.RB 'powersave' |
| 27 | +.br |
| 28 | +.B x86_energy_perf_policy |
| 29 | +.RB [ "\-c cpu" ] |
| 30 | +.RB [ "\-v" ] |
| 31 | +.RB n |
| 32 | +.br |
| 33 | +.SH DESCRIPTION |
| 34 | +\fBx86_energy_perf_policy\fP |
| 35 | +allows software to convey |
| 36 | +its policy for the relative importance of performance |
| 37 | +versus energy savings to the processor. |
| 38 | + |
| 39 | +The processor uses this information in model-specific ways |
| 40 | +when it must select trade-offs between performance and |
| 41 | +energy efficiency. |
| 42 | + |
| 43 | +This policy hint does not supersede Processor Performance states |
| 44 | +(P-states) or CPU Idle power states (C-states), but allows |
| 45 | +software to have influence where it would otherwise be unable |
| 46 | +to express a preference. |
| 47 | + |
| 48 | +For example, this setting may tell the hardware how |
| 49 | +aggressively or conservatively to control frequency |
| 50 | +in the "turbo range" above the explicitly OS-controlled |
| 51 | +P-state frequency range. It may also tell the hardware |
| 52 | +how aggressively is should enter the OS requested C-states. |
| 53 | + |
| 54 | +Support for this feature is indicated by CPUID.06H.ECX.bit3 |
| 55 | +per the Intel Architectures Software Developer's Manual. |
| 56 | + |
| 57 | +.SS Options |
| 58 | +\fB-c\fP limits operation to a single CPU. |
| 59 | +The default is to operate on all CPUs. |
| 60 | +Note that MSR_IA32_ENERGY_PERF_BIAS is defined per |
| 61 | +logical processor, but that the initial implementations |
| 62 | +of the MSR were shared among all processors in each package. |
| 63 | +.PP |
| 64 | +\fB-v\fP increases verbosity. By default |
| 65 | +x86_energy_perf_policy is silent. |
| 66 | +.PP |
| 67 | +\fB-r\fP is for "read-only" mode - the unchanged state |
| 68 | +is read and displayed. |
| 69 | +.PP |
| 70 | +.I performance |
| 71 | +Set a policy where performance is paramount. |
| 72 | +The processor will be unwilling to sacrifice any performance |
| 73 | +for the sake of energy saving. This is the hardware default. |
| 74 | +.PP |
| 75 | +.I normal |
| 76 | +Set a policy with a normal balance between performance and energy efficiency. |
| 77 | +The processor will tolerate minor performance compromise |
| 78 | +for potentially significant energy savings. |
| 79 | +This reasonable default for most desktops and servers. |
| 80 | +.PP |
| 81 | +.I powersave |
| 82 | +Set a policy where the processor can accept |
| 83 | +a measurable performance hit to maximize energy efficiency. |
| 84 | +.PP |
| 85 | +.I n |
| 86 | +Set MSR_IA32_ENERGY_PERF_BIAS to the specified number. |
| 87 | +The range of valid numbers is 0-15, where 0 is maximum |
| 88 | +performance and 15 is maximum energy efficiency. |
| 89 | + |
| 90 | +.SH NOTES |
| 91 | +.B "x86_energy_perf_policy " |
| 92 | +runs only as root. |
| 93 | +.SH FILES |
| 94 | +.ta |
| 95 | +.nf |
| 96 | +/dev/cpu/*/msr |
| 97 | +.fi |
| 98 | + |
| 99 | +.SH "SEE ALSO" |
| 100 | +msr(4) |
| 101 | +.PP |
| 102 | +.SH AUTHORS |
| 103 | +.nf |
| 104 | +Written by Len Brown <len.brown@intel.com> |
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