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torvaldstorvalds
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Merge tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64
Pull ARM64 fixes from Catalin Marinas: - Remove preempt_count modifications in the arm64 IRQ handling code since that's already dealt with in generic irq_enter/irq_exit - PTE_PROT_NONE bit moved higher up to avoid overlapping with the hardware bits (for PROT_NONE mappings which are pte_present) - Big-endian fixes for ptrace support - Asynchronous aborts unmasking while in the kernel - pgprot_writecombine() change to create Normal NonCacheable memory rather than Device GRE * tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: arm64: Move PTE_PROT_NONE higher up arm64: Use Normal NonCacheable memory for writecombine arm64: debug: make aarch32 bkpt checking endian clean arm64: ptrace: fix compat registes get/set to be endian clean arm64: Unmask asynchronous aborts when in kernel mode arm64: dts: Reserve the memory used for secondary CPU release address arm64: let the core code deal with preempt_count
2 parents 033dbbd + 3676f9e commit d5ff835

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8 files changed

+67
-66
lines changed

8 files changed

+67
-66
lines changed

‎arch/arm64/boot/dts/foundation-v8.dts

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,8 @@
66

77
/dts-v1/;
88

9+
/memreserve/ 0x80000000 0x00010000;
10+
911
/ {
1012
model = "Foundation-v8A";
1113
compatible = "arm,foundation-aarch64", "arm,vexpress";

‎arch/arm64/include/asm/irqflags.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,9 @@ static inline void arch_local_irq_disable(void)
5656
#define local_fiq_enable() asm("msr daifclr, #1" : : : "memory")
5757
#define local_fiq_disable() asm("msr daifset, #1" : : : "memory")
5858

59+
#define local_async_enable() asm("msr daifclr, #4" : : : "memory")
60+
#define local_async_disable() asm("msr daifset, #4" : : : "memory")
61+
5962
/*
6063
* Save the current interrupt enable state.
6164
*/

‎arch/arm64/include/asm/pgtable.h

Lines changed: 18 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -25,10 +25,11 @@
2525
* Software defined PTE bits definition.
2626
*/
2727
#define PTE_VALID (_AT(pteval_t, 1) << 0)
28-
#define PTE_PROT_NONE (_AT(pteval_t, 1) << 2) /* only when !PTE_VALID */
29-
#define PTE_FILE (_AT(pteval_t, 1) << 3) /* only when !pte_present() */
28+
#define PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !pte_present() */
3029
#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
3130
#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
31+
/* bit 57 for PMD_SECT_SPLITTING */
32+
#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
3233

3334
/*
3435
* VMALLOC and SPARSEMEM_VMEMMAP ranges.
@@ -254,7 +255,7 @@ static inline int has_transparent_hugepage(void)
254255
#define pgprot_noncached(prot) \
255256
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE))
256257
#define pgprot_writecombine(prot) \
257-
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_GRE))
258+
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
258259
#define pgprot_dmacoherent(prot) \
259260
__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
260261
#define __HAVE_PHYS_MEM_ACCESS_PROT
@@ -357,18 +358,20 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
357358

358359
/*
359360
* Encode and decode a swap entry:
360-
* bits 0, 2: present (must both be zero)
361-
* bit 3: PTE_FILE
362-
* bits 4-8: swap type
363-
* bits 9-63: swap offset
361+
* bits 0-1: present (must be zero)
362+
* bit 2: PTE_FILE
363+
* bits 3-8: swap type
364+
* bits 9-57: swap offset
364365
*/
365-
#define __SWP_TYPE_SHIFT 4
366+
#define __SWP_TYPE_SHIFT 3
366367
#define __SWP_TYPE_BITS 6
368+
#define __SWP_OFFSET_BITS 49
367369
#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
368370
#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
371+
#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
369372

370373
#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
371-
#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
374+
#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
372375
#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
373376

374377
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
@@ -382,15 +385,15 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
382385

383386
/*
384387
* Encode and decode a file entry:
385-
* bits 0, 2: present (must both be zero)
386-
* bit 3: PTE_FILE
387-
* bits 4-63: file offset / PAGE_SIZE
388+
* bits 0-1: present (must be zero)
389+
* bit 2: PTE_FILE
390+
* bits 3-57: file offset / PAGE_SIZE
388391
*/
389392
#define pte_file(pte) (pte_val(pte) & PTE_FILE)
390-
#define pte_to_pgoff(x) (pte_val(x) >> 4)
391-
#define pgoff_to_pte(x) __pte(((x) << 4) | PTE_FILE)
393+
#define pte_to_pgoff(x) (pte_val(x) >> 3)
394+
#define pgoff_to_pte(x) __pte(((x) << 3) | PTE_FILE)
392395

393-
#define PTE_FILE_MAX_BITS 60
396+
#define PTE_FILE_MAX_BITS 55
394397

395398
extern int kern_addr_valid(unsigned long addr);
396399

‎arch/arm64/kernel/debug-monitors.c

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -248,7 +248,8 @@ static int brk_handler(unsigned long addr, unsigned int esr,
248248
int aarch32_break_handler(struct pt_regs *regs)
249249
{
250250
siginfo_t info;
251-
unsigned int instr;
251+
u32 arm_instr;
252+
u16 thumb_instr;
252253
bool bp = false;
253254
void __user *pc = (void __user *)instruction_pointer(regs);
254255

@@ -257,18 +258,21 @@ int aarch32_break_handler(struct pt_regs *regs)
257258

258259
if (compat_thumb_mode(regs)) {
259260
/* get 16-bit Thumb instruction */
260-
get_user(instr, (u16 __user *)pc);
261-
if (instr == AARCH32_BREAK_THUMB2_LO) {
261+
get_user(thumb_instr, (u16 __user *)pc);
262+
thumb_instr = le16_to_cpu(thumb_instr);
263+
if (thumb_instr == AARCH32_BREAK_THUMB2_LO) {
262264
/* get second half of 32-bit Thumb-2 instruction */
263-
get_user(instr, (u16 __user *)(pc + 2));
264-
bp = instr == AARCH32_BREAK_THUMB2_HI;
265+
get_user(thumb_instr, (u16 __user *)(pc + 2));
266+
thumb_instr = le16_to_cpu(thumb_instr);
267+
bp = thumb_instr == AARCH32_BREAK_THUMB2_HI;
265268
} else {
266-
bp = instr == AARCH32_BREAK_THUMB;
269+
bp = thumb_instr == AARCH32_BREAK_THUMB;
267270
}
268271
} else {
269272
/* 32-bit ARM instruction */
270-
get_user(instr, (u32 __user *)pc);
271-
bp = (instr & ~0xf0000000) == AARCH32_BREAK_ARM;
273+
get_user(arm_instr, (u32 __user *)pc);
274+
arm_instr = le32_to_cpu(arm_instr);
275+
bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM;
272276
}
273277

274278
if (!bp)

‎arch/arm64/kernel/entry.S

Lines changed: 7 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -309,15 +309,12 @@ el1_irq:
309309
#ifdef CONFIG_TRACE_IRQFLAGS
310310
bl trace_hardirqs_off
311311
#endif
312-
#ifdef CONFIG_PREEMPT
313-
get_thread_info tsk
314-
ldr w24, [tsk, #TI_PREEMPT] // get preempt count
315-
add w0, w24, #1 // increment it
316-
str w0, [tsk, #TI_PREEMPT]
317-
#endif
312+
318313
irq_handler
314+
319315
#ifdef CONFIG_PREEMPT
320-
str w24, [tsk, #TI_PREEMPT] // restore preempt count
316+
get_thread_info tsk
317+
ldr w24, [tsk, #TI_PREEMPT] // restore preempt count
321318
cbnz w24, 1f // preempt count != 0
322319
ldr x0, [tsk, #TI_FLAGS] // get flags
323320
tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
@@ -507,22 +504,10 @@ el0_irq_naked:
507504
#ifdef CONFIG_TRACE_IRQFLAGS
508505
bl trace_hardirqs_off
509506
#endif
510-
get_thread_info tsk
511-
#ifdef CONFIG_PREEMPT
512-
ldr w24, [tsk, #TI_PREEMPT] // get preempt count
513-
add w23, w24, #1 // increment it
514-
str w23, [tsk, #TI_PREEMPT]
515-
#endif
507+
516508
irq_handler
517-
#ifdef CONFIG_PREEMPT
518-
ldr w0, [tsk, #TI_PREEMPT]
519-
str w24, [tsk, #TI_PREEMPT]
520-
cmp w0, w23
521-
b.eq 1f
522-
mov x1, #0
523-
str x1, [x1] // BUG
524-
1:
525-
#endif
509+
get_thread_info tsk
510+
526511
#ifdef CONFIG_TRACE_IRQFLAGS
527512
bl trace_hardirqs_on
528513
#endif

‎arch/arm64/kernel/ptrace.c

Lines changed: 19 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -636,28 +636,27 @@ static int compat_gpr_get(struct task_struct *target,
636636

637637
for (i = 0; i < num_regs; ++i) {
638638
unsigned int idx = start + i;
639-
void *reg;
639+
compat_ulong_t reg;
640640

641641
switch (idx) {
642642
case 15:
643-
reg = (void *)&task_pt_regs(target)->pc;
643+
reg = task_pt_regs(target)->pc;
644644
break;
645645
case 16:
646-
reg = (void *)&task_pt_regs(target)->pstate;
646+
reg = task_pt_regs(target)->pstate;
647647
break;
648648
case 17:
649-
reg = (void *)&task_pt_regs(target)->orig_x0;
649+
reg = task_pt_regs(target)->orig_x0;
650650
break;
651651
default:
652-
reg = (void *)&task_pt_regs(target)->regs[idx];
652+
reg = task_pt_regs(target)->regs[idx];
653653
}
654654

655-
ret = copy_to_user(ubuf, reg, sizeof(compat_ulong_t));
656-
655+
ret = copy_to_user(ubuf, &reg, sizeof(reg));
657656
if (ret)
658657
break;
659-
else
660-
ubuf += sizeof(compat_ulong_t);
658+
659+
ubuf += sizeof(reg);
661660
}
662661

663662
return ret;
@@ -685,36 +684,35 @@ static int compat_gpr_set(struct task_struct *target,
685684

686685
for (i = 0; i < num_regs; ++i) {
687686
unsigned int idx = start + i;
688-
void *reg;
687+
compat_ulong_t reg;
688+
689+
ret = copy_from_user(&reg, ubuf, sizeof(reg));
690+
if (ret)
691+
return ret;
692+
693+
ubuf += sizeof(reg);
689694

690695
switch (idx) {
691696
case 15:
692-
reg = (void *)&newregs.pc;
697+
newregs.pc = reg;
693698
break;
694699
case 16:
695-
reg = (void *)&newregs.pstate;
700+
newregs.pstate = reg;
696701
break;
697702
case 17:
698-
reg = (void *)&newregs.orig_x0;
703+
newregs.orig_x0 = reg;
699704
break;
700705
default:
701-
reg = (void *)&newregs.regs[idx];
706+
newregs.regs[idx] = reg;
702707
}
703708

704-
ret = copy_from_user(reg, ubuf, sizeof(compat_ulong_t));
705-
706-
if (ret)
707-
goto out;
708-
else
709-
ubuf += sizeof(compat_ulong_t);
710709
}
711710

712711
if (valid_user_regs(&newregs.user_regs))
713712
*task_pt_regs(target) = newregs;
714713
else
715714
ret = -EINVAL;
716715

717-
out:
718716
return ret;
719717
}
720718

‎arch/arm64/kernel/setup.c

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -205,6 +205,11 @@ u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
205205

206206
void __init setup_arch(char **cmdline_p)
207207
{
208+
/*
209+
* Unmask asynchronous aborts early to catch possible system errors.
210+
*/
211+
local_async_enable();
212+
208213
setup_processor();
209214

210215
setup_machine_fdt(__fdt_pointer);

‎arch/arm64/kernel/smp.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -160,6 +160,7 @@ asmlinkage void secondary_start_kernel(void)
160160

161161
local_irq_enable();
162162
local_fiq_enable();
163+
local_async_enable();
163164

164165
/*
165166
* OK, it's off to the idle thread for us

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