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Yongqiang Sunalexdeucher
Yongqiang Sun
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alexdeucher
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drm/amd/display: Refactor for setup periodic interrupt.
[Why] Current periodic interrupt start point calc in optc is not clear. [How] 1. DM convert delta time to lines number and dc will calculate the start position as per lines number and interrupt type. 2. hwss calculates the start point as per line offset. 3. optc programs vertical interrupts register as per start point and interrupt source. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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9 files changed

+215
-151
lines changed

9 files changed

+215
-151
lines changed

‎drivers/gpu/drm/amd/display/dc/core/dc.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1626,13 +1626,13 @@ static void commit_planes_do_stream_update(struct dc *dc,
16261626
stream_update->adjust->v_total_min,
16271627
stream_update->adjust->v_total_max);
16281628

1629-
if (stream_update->periodic_vsync_config && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
1630-
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
1631-
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, VLINE0, &stream->periodic_vsync_config);
1629+
if (stream_update->periodic_interrupt0 &&
1630+
dc->hwss.setup_periodic_interrupt)
1631+
dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0);
16321632

1633-
if (stream_update->enhanced_sync_config && pipe_ctx->stream_res.tg->funcs->program_vline_interrupt)
1634-
pipe_ctx->stream_res.tg->funcs->program_vline_interrupt(
1635-
pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing, VLINE1, &stream->enhanced_sync_config);
1633+
if (stream_update->periodic_interrupt1 &&
1634+
dc->hwss.setup_periodic_interrupt)
1635+
dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE1);
16361636

16371637
if ((stream_update->hdr_static_metadata && !stream->use_dynamic_meta) ||
16381638
stream_update->vrr_infopacket ||

‎drivers/gpu/drm/amd/display/dc/dc_stream.h

Lines changed: 17 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -51,9 +51,19 @@ struct freesync_context {
5151
bool dummy;
5252
};
5353

54-
union vline_config {
55-
unsigned int line_number;
56-
unsigned long long delta_in_ns;
54+
enum vertical_interrupt_ref_point {
55+
START_V_UPDATE = 0,
56+
START_V_SYNC,
57+
INVALID_POINT
58+
59+
//For now, only v_update interrupt is used.
60+
//START_V_BLANK,
61+
//START_V_ACTIVE
62+
};
63+
64+
struct periodic_interrupt_config {
65+
enum vertical_interrupt_ref_point ref_point;
66+
int lines_offset;
5767
};
5868

5969

@@ -106,8 +116,8 @@ struct dc_stream_state {
106116
/* DMCU info */
107117
unsigned int abm_level;
108118

109-
union vline_config periodic_vsync_config;
110-
union vline_config enhanced_sync_config;
119+
struct periodic_interrupt_config periodic_interrupt0;
120+
struct periodic_interrupt_config periodic_interrupt1;
111121

112122
/* from core_stream struct */
113123
struct dc_context *ctx;
@@ -158,8 +168,8 @@ struct dc_stream_update {
158168
struct dc_info_packet *hdr_static_metadata;
159169
unsigned int *abm_level;
160170

161-
union vline_config *periodic_vsync_config;
162-
union vline_config *enhanced_sync_config;
171+
struct periodic_interrupt_config *periodic_interrupt0;
172+
struct periodic_interrupt_config *periodic_interrupt1;
163173

164174
struct dc_crtc_timing_adjust *adjust;
165175
struct dc_info_packet *vrr_infopacket;

‎drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1333,10 +1333,8 @@ static enum dc_status apply_single_controller_ctx_to_hw(
13331333
if (!pipe_ctx->stream->apply_seamless_boot_optimization)
13341334
dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
13351335

1336-
if (pipe_ctx->stream_res.tg->funcs->program_vupdate_interrupt)
1337-
pipe_ctx->stream_res.tg->funcs->program_vupdate_interrupt(
1338-
pipe_ctx->stream_res.tg,
1339-
&stream->timing);
1336+
if (dc->hwss.setup_vupdate_interrupt)
1337+
dc->hwss.setup_vupdate_interrupt(pipe_ctx);
13401338

13411339
params.vertical_total_min = stream->adjust.v_total_min;
13421340
params.vertical_total_max = stream->adjust.v_total_max;

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

Lines changed: 144 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2741,6 +2741,147 @@ static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
27412741
pipe_ctx->plane_res.dpp, &opt_attr);
27422742
}
27432743

2744+
/**
2745+
* apply_front_porch_workaround TODO FPGA still need?
2746+
*
2747+
* This is a workaround for a bug that has existed since R5xx and has not been
2748+
* fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
2749+
*/
2750+
static void apply_front_porch_workaround(
2751+
struct dc_crtc_timing *timing)
2752+
{
2753+
if (timing->flags.INTERLACE == 1) {
2754+
if (timing->v_front_porch < 2)
2755+
timing->v_front_porch = 2;
2756+
} else {
2757+
if (timing->v_front_porch < 1)
2758+
timing->v_front_porch = 1;
2759+
}
2760+
}
2761+
2762+
int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
2763+
{
2764+
struct timing_generator *optc = pipe_ctx->stream_res.tg;
2765+
const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
2766+
struct dc_crtc_timing patched_crtc_timing;
2767+
int vesa_sync_start;
2768+
int asic_blank_end;
2769+
int interlace_factor;
2770+
int vertical_line_start;
2771+
2772+
patched_crtc_timing = *dc_crtc_timing;
2773+
apply_front_porch_workaround(&patched_crtc_timing);
2774+
2775+
interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
2776+
2777+
vesa_sync_start = patched_crtc_timing.v_addressable +
2778+
patched_crtc_timing.v_border_bottom +
2779+
patched_crtc_timing.v_front_porch;
2780+
2781+
asic_blank_end = (patched_crtc_timing.v_total -
2782+
vesa_sync_start -
2783+
patched_crtc_timing.v_border_top)
2784+
* interlace_factor;
2785+
2786+
vertical_line_start = asic_blank_end -
2787+
optc->dlg_otg_param.vstartup_start + 1;
2788+
2789+
return vertical_line_start;
2790+
}
2791+
2792+
static void calc_vupdate_position(
2793+
struct pipe_ctx *pipe_ctx,
2794+
uint32_t *start_line,
2795+
uint32_t *end_line)
2796+
{
2797+
const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
2798+
int vline_int_offset_from_vupdate =
2799+
pipe_ctx->stream->periodic_interrupt0.lines_offset;
2800+
int vupdate_offset_from_vsync = get_vupdate_offset_from_vsync(pipe_ctx);
2801+
int start_position;
2802+
2803+
if (vline_int_offset_from_vupdate > 0)
2804+
vline_int_offset_from_vupdate--;
2805+
else if (vline_int_offset_from_vupdate < 0)
2806+
vline_int_offset_from_vupdate++;
2807+
2808+
start_position = vline_int_offset_from_vupdate + vupdate_offset_from_vsync;
2809+
2810+
if (start_position >= 0)
2811+
*start_line = start_position;
2812+
else
2813+
*start_line = dc_crtc_timing->v_total + start_position - 1;
2814+
2815+
*end_line = *start_line + 2;
2816+
2817+
if (*end_line >= dc_crtc_timing->v_total)
2818+
*end_line = 2;
2819+
}
2820+
2821+
static void cal_vline_position(
2822+
struct pipe_ctx *pipe_ctx,
2823+
enum vline_select vline,
2824+
uint32_t *start_line,
2825+
uint32_t *end_line)
2826+
{
2827+
enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
2828+
2829+
if (vline == VLINE0)
2830+
ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
2831+
else if (vline == VLINE1)
2832+
ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
2833+
2834+
switch (ref_point) {
2835+
case START_V_UPDATE:
2836+
calc_vupdate_position(
2837+
pipe_ctx,
2838+
start_line,
2839+
end_line);
2840+
break;
2841+
case START_V_SYNC:
2842+
// Suppose to do nothing because vsync is 0;
2843+
break;
2844+
default:
2845+
ASSERT(0);
2846+
break;
2847+
}
2848+
}
2849+
2850+
static void dcn10_setup_periodic_interrupt(
2851+
struct pipe_ctx *pipe_ctx,
2852+
enum vline_select vline)
2853+
{
2854+
struct timing_generator *tg = pipe_ctx->stream_res.tg;
2855+
2856+
if (vline == VLINE0) {
2857+
uint32_t start_line = 0;
2858+
uint32_t end_line = 0;
2859+
2860+
cal_vline_position(pipe_ctx, vline, &start_line, &end_line);
2861+
2862+
tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
2863+
2864+
} else if (vline == VLINE1) {
2865+
pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
2866+
tg,
2867+
pipe_ctx->stream->periodic_interrupt1.lines_offset);
2868+
}
2869+
}
2870+
2871+
static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
2872+
{
2873+
struct timing_generator *tg = pipe_ctx->stream_res.tg;
2874+
int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
2875+
2876+
if (start_line < 0) {
2877+
ASSERT(0);
2878+
start_line = 0;
2879+
}
2880+
2881+
if (tg->funcs->setup_vertical_interrupt2)
2882+
tg->funcs->setup_vertical_interrupt2(tg, start_line);
2883+
}
2884+
27442885
static const struct hw_sequencer_funcs dcn10_funcs = {
27452886
.program_gamut_remap = program_gamut_remap,
27462887
.init_hw = dcn10_init_hw,
@@ -2790,7 +2931,9 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
27902931
.set_cursor_attribute = dcn10_set_cursor_attribute,
27912932
.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
27922933
.disable_stream_gating = NULL,
2793-
.enable_stream_gating = NULL
2934+
.enable_stream_gating = NULL,
2935+
.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
2936+
.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt
27942937
};
27952938

27962939

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,4 +81,6 @@ struct pipe_ctx *find_top_pipe_for_stream(
8181
struct dc_state *context,
8282
const struct dc_stream_state *stream);
8383

84+
int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx);
85+
8486
#endif /* __DC_HWSS_DCN10_H__ */

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