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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull late ARM SoC updates from Kevin Hilman: "This is a collection of a few late fixes and other misc stuff that had dependencies on things being merged from other trees. The bulk of the changes are for samsung/exynos SoCs for some changes that needed a few minor reworks so ended up a bit late. The others are mainly for qcom SoCs: a couple fixes and some DTS updates" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (37 commits) ARM: multi_v7_defconfig: Enable PBIAS regulator soc: qcom: smd: Correct fBLOCKREADINTR handling soc: qcom: smd: Use correct remote processor ID soc: qcom: smem: Fix errant private access ARM: dts: qcom: msm8974-sony-xperia-honami: Use stdout-path ARM: dts: qcom: msm8960-cdp: Use stdout-path ARM: dts: qcom: msm8660-surf: Use stdout-path ARM: dts: qcom: ipq8064-ap148: Use stdout-path ARM: dts: qcom: apq8084-mtp: Use stdout-path ARM: dts: qcom: apq8084-ifc6540: Use stdout-path ARM: dts: qcom: apq8074-dragonboard: Use stdout-path ARM: dts: qcom: apq8064-ifc6410: Use stdout-path ARM: dts: qcom: apq8064-cm-qs600: Use stdout-path ARM: dts: qcom: Label serial nodes for aliasing and stdout-path reset: ath79: Fix missing spin_lock_init reset: Add (devm_)reset_control_get stub functions ARM: EXYNOS: switch to using generic cpufreq driver for exynos4x12 cpufreq: exynos: Remove unselectable rule for arm-exynos-cpufreq.o ARM: dts: add iommu property to JPEG device for exynos4 ARM: dts: enable SPI1 for exynos4412-odroidu3 ...
2 parents 519f526 + c6e59bd commit d71fc23

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‎Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt

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@@ -37,6 +37,12 @@ The edge is described by the following properties:
3737
Definition: the identifier of the remote processor in the smd channel
3838
allocation table
3939

40+
- qcom,remote-pid:
41+
Usage: optional
42+
Value type: <u32>
43+
Definition: the identifier for the remote processor as known by the rest
44+
of the system.
45+
4046
= SMD DEVICES
4147

4248
In turn, subnodes of the "edges" represent devices tied to SMD channels on that

‎arch/arm/boot/dts/exynos3250-monk.dts

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@@ -116,6 +116,21 @@
116116
min-microvolt = <1100000>;
117117
max-microvolt = <2700000>;
118118
};
119+
120+
thermal-zones {
121+
cpu_thermal: cpu-thermal {
122+
cooling-maps {
123+
map0 {
124+
/* Correspond to 500MHz at freq_table */
125+
cooling-device = <&cpu0 5 5>;
126+
};
127+
map1 {
128+
/* Correspond to 200MHz at freq_table */
129+
cooling-device = <&cpu0 8 8>;
130+
};
131+
};
132+
};
133+
};
119134
};
120135

121136
&adc {
@@ -141,6 +156,10 @@
141156
};
142157
};
143158

159+
&cpu0 {
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cpu0-supply = <&buck2_reg>;
161+
};
162+
144163
&exynos_usbphy {
145164
status = "okay";
146165
};

‎arch/arm/boot/dts/exynos3250-rinato.dts

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@@ -107,6 +107,21 @@
107107
min-microvolt = <1100000>;
108108
max-microvolt = <2700000>;
109109
};
110+
111+
thermal-zones {
112+
cpu_thermal: cpu-thermal {
113+
cooling-maps {
114+
map0 {
115+
/* Corresponds to 500MHz */
116+
cooling-device = <&cpu0 5 5>;
117+
};
118+
map1 {
119+
/* Corresponds to 200MHz */
120+
cooling-device = <&cpu0 8 8>;
121+
};
122+
};
123+
};
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};
110125
};
111126

112127
&adc {
@@ -132,6 +147,10 @@
132147
};
133148
};
134149

150+
&cpu0 {
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cpu0-supply = <&buck2_reg>;
152+
};
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135154
&exynos_usbphy {
136155
status = "okay";
137156
};

‎arch/arm/boot/dts/exynos3250.dtsi

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@@ -53,6 +53,22 @@
5353
compatible = "arm,cortex-a7";
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reg = <0>;
5555
clock-frequency = <1000000000>;
56+
clocks = <&cmu CLK_ARM_CLK>;
57+
clock-names = "cpu";
58+
#cooling-cells = <2>;
59+
60+
operating-points = <
61+
1000000 1150000
62+
900000 1112500
63+
800000 1075000
64+
700000 1037500
65+
600000 1000000
66+
500000 962500
67+
400000 925000
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300000 887500
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200000 850000
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100000 850000
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>;
5672
};
5773

5874
cpu1: cpu@1 {

‎arch/arm/boot/dts/exynos4.dtsi

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@@ -702,6 +702,7 @@
702702
clocks = <&clock CLK_JPEG>;
703703
clock-names = "jpeg";
704704
power-domains = <&pd_cam>;
705+
iommus = <&sysmmu_jpeg>;
705706
};
706707

707708
hdmi: hdmi@12D00000 {

‎arch/arm/boot/dts/exynos4212.dtsi

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@@ -30,6 +30,9 @@
3030
device_type = "cpu";
3131
compatible = "arm,cortex-a9";
3232
reg = <0xA00>;
33+
clocks = <&clock CLK_ARM_CLK>;
34+
clock-names = "cpu";
35+
operating-points-v2 = <&cpu0_opp_table>;
3336
cooling-min-level = <13>;
3437
cooling-max-level = <7>;
3538
#cooling-cells = <2>; /* min followed by max */
@@ -39,6 +42,84 @@
3942
device_type = "cpu";
4043
compatible = "arm,cortex-a9";
4144
reg = <0xA01>;
45+
operating-points-v2 = <&cpu0_opp_table>;
46+
};
47+
};
48+
49+
cpu0_opp_table: opp_table0 {
50+
compatible = "operating-points-v2";
51+
opp-shared;
52+
53+
opp00 {
54+
opp-hz = /bits/ 64 <200000000>;
55+
opp-microvolt = <900000>;
56+
clock-latency-ns = <200000>;
57+
};
58+
opp01 {
59+
opp-hz = /bits/ 64 <300000000>;
60+
opp-microvolt = <900000>;
61+
clock-latency-ns = <200000>;
62+
};
63+
opp02 {
64+
opp-hz = /bits/ 64 <400000000>;
65+
opp-microvolt = <925000>;
66+
clock-latency-ns = <200000>;
67+
};
68+
opp03 {
69+
opp-hz = /bits/ 64 <500000000>;
70+
opp-microvolt = <950000>;
71+
clock-latency-ns = <200000>;
72+
};
73+
opp04 {
74+
opp-hz = /bits/ 64 <600000000>;
75+
opp-microvolt = <975000>;
76+
clock-latency-ns = <200000>;
77+
};
78+
opp05 {
79+
opp-hz = /bits/ 64 <700000000>;
80+
opp-microvolt = <987500>;
81+
clock-latency-ns = <200000>;
82+
};
83+
opp06 {
84+
opp-hz = /bits/ 64 <800000000>;
85+
opp-microvolt = <1000000>;
86+
clock-latency-ns = <200000>;
87+
};
88+
opp07 {
89+
opp-hz = /bits/ 64 <900000000>;
90+
opp-microvolt = <1037500>;
91+
clock-latency-ns = <200000>;
92+
};
93+
opp08 {
94+
opp-hz = /bits/ 64 <1000000000>;
95+
opp-microvolt = <1087500>;
96+
clock-latency-ns = <200000>;
97+
};
98+
opp09 {
99+
opp-hz = /bits/ 64 <1100000000>;
100+
opp-microvolt = <1137500>;
101+
clock-latency-ns = <200000>;
102+
};
103+
opp10 {
104+
opp-hz = /bits/ 64 <1200000000>;
105+
opp-microvolt = <1187500>;
106+
clock-latency-ns = <200000>;
107+
};
108+
opp11 {
109+
opp-hz = /bits/ 64 <1300000000>;
110+
opp-microvolt = <1250000>;
111+
clock-latency-ns = <200000>;
112+
};
113+
opp12 {
114+
opp-hz = /bits/ 64 <1400000000>;
115+
opp-microvolt = <1287500>;
116+
clock-latency-ns = <200000>;
117+
};
118+
opp13 {
119+
opp-hz = /bits/ 64 <1500000000>;
120+
opp-microvolt = <1350000>;
121+
clock-latency-ns = <200000>;
122+
turbo-mode;
42123
};
43124
};
44125
};

‎arch/arm/boot/dts/exynos4412-odroid-common.dtsi

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@@ -107,6 +107,10 @@
107107
};
108108
};
109109

110+
&cpu0 {
111+
cpu0-supply = <&buck2_reg>;
112+
};
113+
110114
/* RSTN signal for eMMC */
111115
&sd1_cd {
112116
samsung,pin-pud = <0>;

‎arch/arm/boot/dts/exynos4412-odroidu3.dts

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@@ -13,6 +13,7 @@
1313

1414
/dts-v1/;
1515
#include "exynos4412-odroid-common.dtsi"
16+
#include <dt-bindings/gpio/gpio.h>
1617

1718
/ {
1819
model = "Hardkernel ODROID-U3 board based on Exynos4412";
@@ -61,3 +62,10 @@
6162
"Speakers", "SPKL",
6263
"Speakers", "SPKR";
6364
};
65+
66+
&spi_1 {
67+
pinctrl-names = "default";
68+
pinctrl-0 = <&spi1_bus>;
69+
cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>;
70+
status = "okay";
71+
};

‎arch/arm/boot/dts/exynos4412-origen.dts

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@@ -78,6 +78,10 @@
7878
};
7979
};
8080

81+
&cpu0 {
82+
cpu0-supply = <&buck2_reg>;
83+
};
84+
8185
&fimd {
8286
pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
8387
pinctrl-names = "default";

‎arch/arm/boot/dts/exynos4412-trats2.dts

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288288
status = "okay";
289289
};
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291+
&cpu0 {
292+
cpu0-supply = <&buck2_reg>;
293+
};
294+
291295
&csis_0 {
292296
status = "okay";
293297
vddcore-supply = <&ldo8_reg>;

‎arch/arm/boot/dts/exynos4412.dtsi

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@@ -30,6 +30,9 @@
3030
device_type = "cpu";
3131
compatible = "arm,cortex-a9";
3232
reg = <0xA00>;
33+
clocks = <&clock CLK_ARM_CLK>;
34+
clock-names = "cpu";
35+
operating-points-v2 = <&cpu0_opp_table>;
3336
cooling-min-level = <13>;
3437
cooling-max-level = <7>;
3538
#cooling-cells = <2>; /* min followed by max */
@@ -39,18 +42,98 @@
3942
device_type = "cpu";
4043
compatible = "arm,cortex-a9";
4144
reg = <0xA01>;
45+
operating-points-v2 = <&cpu0_opp_table>;
4246
};
4347

4448
cpu@A02 {
4549
device_type = "cpu";
4650
compatible = "arm,cortex-a9";
4751
reg = <0xA02>;
52+
operating-points-v2 = <&cpu0_opp_table>;
4853
};
4954

5055
cpu@A03 {
5156
device_type = "cpu";
5257
compatible = "arm,cortex-a9";
5358
reg = <0xA03>;
59+
operating-points-v2 = <&cpu0_opp_table>;
60+
};
61+
};
62+
63+
cpu0_opp_table: opp_table0 {
64+
compatible = "operating-points-v2";
65+
opp-shared;
66+
67+
opp00 {
68+
opp-hz = /bits/ 64 <200000000>;
69+
opp-microvolt = <900000>;
70+
clock-latency-ns = <200000>;
71+
};
72+
opp01 {
73+
opp-hz = /bits/ 64 <300000000>;
74+
opp-microvolt = <900000>;
75+
clock-latency-ns = <200000>;
76+
};
77+
opp02 {
78+
opp-hz = /bits/ 64 <400000000>;
79+
opp-microvolt = <925000>;
80+
clock-latency-ns = <200000>;
81+
};
82+
opp03 {
83+
opp-hz = /bits/ 64 <500000000>;
84+
opp-microvolt = <950000>;
85+
clock-latency-ns = <200000>;
86+
};
87+
opp04 {
88+
opp-hz = /bits/ 64 <600000000>;
89+
opp-microvolt = <975000>;
90+
clock-latency-ns = <200000>;
91+
};
92+
opp05 {
93+
opp-hz = /bits/ 64 <700000000>;
94+
opp-microvolt = <987500>;
95+
clock-latency-ns = <200000>;
96+
};
97+
opp06 {
98+
opp-hz = /bits/ 64 <800000000>;
99+
opp-microvolt = <1000000>;
100+
clock-latency-ns = <200000>;
101+
};
102+
opp07 {
103+
opp-hz = /bits/ 64 <900000000>;
104+
opp-microvolt = <1037500>;
105+
clock-latency-ns = <200000>;
106+
};
107+
opp08 {
108+
opp-hz = /bits/ 64 <1000000000>;
109+
opp-microvolt = <1087500>;
110+
clock-latency-ns = <200000>;
111+
};
112+
opp09 {
113+
opp-hz = /bits/ 64 <1100000000>;
114+
opp-microvolt = <1137500>;
115+
clock-latency-ns = <200000>;
116+
};
117+
opp10 {
118+
opp-hz = /bits/ 64 <1200000000>;
119+
opp-microvolt = <1187500>;
120+
clock-latency-ns = <200000>;
121+
};
122+
opp11 {
123+
opp-hz = /bits/ 64 <1300000000>;
124+
opp-microvolt = <1250000>;
125+
clock-latency-ns = <200000>;
126+
};
127+
opp12 {
128+
opp-hz = /bits/ 64 <1400000000>;
129+
opp-microvolt = <1287500>;
130+
clock-latency-ns = <200000>;
131+
};
132+
opp13 {
133+
opp-hz = /bits/ 64 <1500000000>;
134+
opp-microvolt = <1350000>;
135+
clock-latency-ns = <200000>;
136+
turbo-mode;
54137
};
55138
};
56139

‎arch/arm/boot/dts/exynos5250-arndale.dts

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117117
};
118118
};
119119

120+
&cpu0 {
121+
cpu0-supply = <&buck2_reg>;
122+
};
123+
120124
&dp {
121125
status = "okay";
122126
samsung,color-space = <0>;

‎arch/arm/boot/dts/exynos5250-smdk5250.dts

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7474
};
7575
};
7676

77+
&cpu0 {
78+
cpu0-supply = <&buck2_reg>;
79+
};
80+
7781
&dp {
7882
samsung,color-space = <0>;
7983
samsung,dynamic-range = <0>;

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