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mahesh1krrodrigovivi
mahesh1kr
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rodrigovivi
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drm/i915/icl: Combine all port/combophy macros at one place
This patch combines CNL/ICL specific port/combophy macros together at one location. This is prework for patches later in series where new macros to find port/combophy register will be introduced. v2: remove wrong empty line Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181012234717.8284-1-lucas.demarchi@intel.com
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‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 72 additions & 65 deletions
Original file line numberDiff line numberDiff line change
@@ -1631,14 +1631,41 @@ enum i915_power_well_id {
16311631
#define PHY_RESERVED (1 << 7)
16321632
#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
16331633

1634-
#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
1635-
#define CL_POWER_DOWN_ENABLE (1 << 4)
1636-
#define SUS_CLOCK_CONFIG (3 << 0)
1634+
#define _PORT_CL1CM_DW9_A 0x162024
1635+
#define _PORT_CL1CM_DW9_BC 0x6C024
1636+
#define IREF0RC_OFFSET_SHIFT 8
1637+
#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1638+
#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
16371639

1640+
#define _PORT_CL1CM_DW10_A 0x162028
1641+
#define _PORT_CL1CM_DW10_BC 0x6C028
1642+
#define IREF1RC_OFFSET_SHIFT 8
1643+
#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1644+
#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1645+
1646+
#define _PORT_CL1CM_DW28_A 0x162070
1647+
#define _PORT_CL1CM_DW28_BC 0x6C070
1648+
#define OCL1_POWER_DOWN_EN (1 << 23)
1649+
#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1650+
#define SUS_CLK_CONFIG 0x3
1651+
#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1652+
1653+
#define _PORT_CL1CM_DW30_A 0x162078
1654+
#define _PORT_CL1CM_DW30_BC 0x6C078
1655+
#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1656+
#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1657+
1658+
/*
1659+
* CNL/ICL Port/COMBO-PHY Registers
1660+
*/
1661+
/* CNL/ICL Port CL_DW registers */
1662+
#define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
16381663
#define _ICL_PORT_CL_DW5_A 0x162014
16391664
#define _ICL_PORT_CL_DW5_B 0x6C014
16401665
#define ICL_PORT_CL_DW5(port) _MMIO_PORT(port, _ICL_PORT_CL_DW5_A, \
16411666
_ICL_PORT_CL_DW5_B)
1667+
#define CL_POWER_DOWN_ENABLE (1 << 4)
1668+
#define SUS_CLOCK_CONFIG (3 << 0)
16421669

16431670
#define _CNL_PORT_CL_DW10_A 0x162028
16441671
#define _ICL_PORT_CL_DW10_B 0x6c028
@@ -1660,37 +1687,56 @@ enum i915_power_well_id {
16601687
#define PWR_DOWN_LN_MASK (0xf << 4)
16611688
#define PWR_DOWN_LN_SHIFT 4
16621689

1663-
#define _PORT_CL1CM_DW9_A 0x162024
1664-
#define _PORT_CL1CM_DW9_BC 0x6C024
1665-
#define IREF0RC_OFFSET_SHIFT 8
1666-
#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
1667-
#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
1668-
1669-
#define _PORT_CL1CM_DW10_A 0x162028
1670-
#define _PORT_CL1CM_DW10_BC 0x6C028
1671-
#define IREF1RC_OFFSET_SHIFT 8
1672-
#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
1673-
#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
1674-
16751690
#define _ICL_PORT_CL_DW12_A 0x162030
16761691
#define _ICL_PORT_CL_DW12_B 0x6C030
16771692
#define ICL_LANE_ENABLE_AUX (1 << 0)
16781693
#define ICL_PORT_CL_DW12(port) _MMIO_PORT((port), \
16791694
_ICL_PORT_CL_DW12_A, \
16801695
_ICL_PORT_CL_DW12_B)
16811696

1682-
#define _PORT_CL1CM_DW28_A 0x162070
1683-
#define _PORT_CL1CM_DW28_BC 0x6C070
1684-
#define OCL1_POWER_DOWN_EN (1 << 23)
1685-
#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
1686-
#define SUS_CLK_CONFIG 0x3
1687-
#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
1697+
/* CNL/ICL Port COMP_DW registers */
1698+
#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
1699+
#define _ICL_PORT_COMP_DW0_A 0x162100
1700+
#define _ICL_PORT_COMP_DW0_B 0x6C100
1701+
#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
1702+
_ICL_PORT_COMP_DW0_B)
1703+
#define COMP_INIT (1 << 31)
16881704

1689-
#define _PORT_CL1CM_DW30_A 0x162078
1690-
#define _PORT_CL1CM_DW30_BC 0x6C078
1691-
#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
1692-
#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
1705+
#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
1706+
#define _ICL_PORT_COMP_DW1_A 0x162104
1707+
#define _ICL_PORT_COMP_DW1_B 0x6C104
1708+
#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
1709+
_ICL_PORT_COMP_DW1_B)
1710+
#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
1711+
#define _ICL_PORT_COMP_DW3_A 0x16210C
1712+
#define _ICL_PORT_COMP_DW3_B 0x6C10C
1713+
#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
1714+
_ICL_PORT_COMP_DW3_B)
1715+
#define PROCESS_INFO_DOT_0 (0 << 26)
1716+
#define PROCESS_INFO_DOT_1 (1 << 26)
1717+
#define PROCESS_INFO_DOT_4 (2 << 26)
1718+
#define PROCESS_INFO_MASK (7 << 26)
1719+
#define PROCESS_INFO_SHIFT 26
1720+
#define VOLTAGE_INFO_0_85V (0 << 24)
1721+
#define VOLTAGE_INFO_0_95V (1 << 24)
1722+
#define VOLTAGE_INFO_1_05V (2 << 24)
1723+
#define VOLTAGE_INFO_MASK (3 << 24)
1724+
#define VOLTAGE_INFO_SHIFT 24
1725+
1726+
#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
1727+
#define _ICL_PORT_COMP_DW9_A 0x162124
1728+
#define _ICL_PORT_COMP_DW9_B 0x6C124
1729+
#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
1730+
_ICL_PORT_COMP_DW9_B)
1731+
1732+
#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
1733+
#define _ICL_PORT_COMP_DW10_A 0x162128
1734+
#define _ICL_PORT_COMP_DW10_B 0x6C128
1735+
#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
1736+
_ICL_PORT_COMP_DW10_A, \
1737+
_ICL_PORT_COMP_DW10_B)
16931738

1739+
/* CNL/ICL Port PCS registers */
16941740
#define _CNL_PORT_PCS_DW1_GRP_AE 0x162304
16951741
#define _CNL_PORT_PCS_DW1_GRP_B 0x162384
16961742
#define _CNL_PORT_PCS_DW1_GRP_C 0x162B04
@@ -1734,7 +1780,7 @@ enum i915_power_well_id {
17341780
_ICL_PORT_PCS_DW1_AUX_B)
17351781
#define COMMON_KEEPER_EN (1 << 26)
17361782

1737-
/* CNL Port TX registers */
1783+
/* CNL/ICL Port TX registers */
17381784
#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
17391785
#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
17401786
#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
@@ -2054,45 +2100,6 @@ enum i915_power_well_id {
20542100
#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
20552101
#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
20562102

2057-
#define CNL_PORT_COMP_DW0 _MMIO(0x162100)
2058-
#define COMP_INIT (1 << 31)
2059-
#define CNL_PORT_COMP_DW1 _MMIO(0x162104)
2060-
#define CNL_PORT_COMP_DW3 _MMIO(0x16210c)
2061-
#define PROCESS_INFO_DOT_0 (0 << 26)
2062-
#define PROCESS_INFO_DOT_1 (1 << 26)
2063-
#define PROCESS_INFO_DOT_4 (2 << 26)
2064-
#define PROCESS_INFO_MASK (7 << 26)
2065-
#define PROCESS_INFO_SHIFT 26
2066-
#define VOLTAGE_INFO_0_85V (0 << 24)
2067-
#define VOLTAGE_INFO_0_95V (1 << 24)
2068-
#define VOLTAGE_INFO_1_05V (2 << 24)
2069-
#define VOLTAGE_INFO_MASK (3 << 24)
2070-
#define VOLTAGE_INFO_SHIFT 24
2071-
#define CNL_PORT_COMP_DW9 _MMIO(0x162124)
2072-
#define CNL_PORT_COMP_DW10 _MMIO(0x162128)
2073-
2074-
#define _ICL_PORT_COMP_DW0_A 0x162100
2075-
#define _ICL_PORT_COMP_DW0_B 0x6C100
2076-
#define ICL_PORT_COMP_DW0(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW0_A, \
2077-
_ICL_PORT_COMP_DW0_B)
2078-
#define _ICL_PORT_COMP_DW1_A 0x162104
2079-
#define _ICL_PORT_COMP_DW1_B 0x6C104
2080-
#define ICL_PORT_COMP_DW1(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW1_A, \
2081-
_ICL_PORT_COMP_DW1_B)
2082-
#define _ICL_PORT_COMP_DW3_A 0x16210C
2083-
#define _ICL_PORT_COMP_DW3_B 0x6C10C
2084-
#define ICL_PORT_COMP_DW3(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW3_A, \
2085-
_ICL_PORT_COMP_DW3_B)
2086-
#define _ICL_PORT_COMP_DW9_A 0x162124
2087-
#define _ICL_PORT_COMP_DW9_B 0x6C124
2088-
#define ICL_PORT_COMP_DW9(port) _MMIO_PORT(port, _ICL_PORT_COMP_DW9_A, \
2089-
_ICL_PORT_COMP_DW9_B)
2090-
#define _ICL_PORT_COMP_DW10_A 0x162128
2091-
#define _ICL_PORT_COMP_DW10_B 0x6C128
2092-
#define ICL_PORT_COMP_DW10(port) _MMIO_PORT(port, \
2093-
_ICL_PORT_COMP_DW10_A, \
2094-
_ICL_PORT_COMP_DW10_B)
2095-
20962103
/* ICL PHY DFLEX registers */
20972104
#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
20982105
#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))

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