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Merge tag 'spi-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown: "This is quite a quiet release but some new drivers mean that the diffstat is fairly large. The new drivers include the aspeed driver which is migrated from MTD as part of the ongoing move of controllers with specialised support for SPI flashes into the SPI subsystem. - Support for devices which flip CPHA during recieve only transfers (eg, if MOSI and MISO have inverted polarity). - Overhaul of the i.MX driver, including the addition of PIO support for better performance on small transfers. - Migration of the Aspeed driver from MTD. - Support for Aspeed AST2400, Ingenic JZ4775 and X1/2000 and MediaTek IPM and SFI" * tag 'spi-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (84 commits) spi: spi-au1550: replace ternary operator with min() mtd: spi-nor: aspeed: set the decoding size to at least 2MB for AST2600 spi: aspeed: Calibrate read timings spi: aspeed: Add support for the AST2400 SPI controller spi: aspeed: Workaround AST2500 limitations spi: aspeed: Adjust direct mapping to device size spi: aspeed: Add support for direct mapping spi: spi-mem: Convert Aspeed SMC driver to spi-mem spi: Convert the Aspeed SMC controllers device tree binding spi: spi-cadence: Update ISR status variable type to irqreturn_t spi: Doc fix - Describe add_lock and dma_map_dev in spi_controller spi: cadence-quadspi: Handle spi_unregister_master() in remove() spi: stm32-qspi: Remove SR_BUSY bit check before sending command spi: stm32-qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd() spi: stm32-qspi: Fix wait_cmd timeout in APM mode spi: cadence-quadspi: remove unnecessary (void *) casts spi: cadence-quadspi: Add missing blank line in cqspi_request_mmap_dma() spi: spi-imx: mx51_ecspi_prepare_message(): skip writing MX51_ECSPI_CONFIG register if unchanged spi: spi-imx: add PIO polling support spi: spi-imx: replace struct spi_imx_data::bitbang by pointer to struct spi_controller ...
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‎Documentation/devicetree/bindings/mtd/aspeed-smc.txt

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‎Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/aspeed,ast2600-fmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Aspeed SMC controllers bindings
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maintainers:
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- Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
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- Cédric Le Goater <clg@kaod.org>
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description: |
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This binding describes the Aspeed Static Memory Controllers (FMC and
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SPI) of the AST2400, AST2500 and AST2600 SOCs.
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allOf:
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- $ref: "spi-controller.yaml#"
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properties:
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compatible:
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enum:
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- aspeed,ast2600-fmc
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- aspeed,ast2600-spi
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- aspeed,ast2500-fmc
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- aspeed,ast2500-spi
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- aspeed,ast2400-fmc
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- aspeed,ast2400-spi
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reg:
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items:
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- description: registers
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- description: memory mapping
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h>
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#include <dt-bindings/clock/ast2600-clock.h>
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spi@1e620000 {
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reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "aspeed,ast2600-fmc";
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clocks = <&syscon ASPEED_CLK_AHB>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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flash@0 {
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reg = < 0 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <2>;
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};
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flash@1 {
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reg = < 1 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <2>;
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};
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flash@2 {
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reg = < 2 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <2>;
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};
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};

‎Documentation/devicetree/bindings/spi/ingenic,spi.yaml

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oneOf:
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- enum:
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- ingenic,jz4750-spi
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- ingenic,jz4775-spi
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- ingenic,jz4780-spi
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- ingenic,x1000-spi
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- ingenic,x2000-spi
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- items:
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- enum:
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- ingenic,jz4760-spi

‎Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml

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maxItems: 1
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clocks:
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minItems: 3
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items:
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- description: clock used for the parent clock
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- description: clock used for the muxes clock
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- description: clock used for the clock gate
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- description: clock used for the AHB bus, this clock is optional
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clock-names:
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minItems: 3
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items:
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- const: parent-clk
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- const: sel-clk
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- const: spi-clk
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- const: hclk
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mediatek,pad-select:
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$ref: /schemas/types.yaml#/definitions/uint32-array

‎Documentation/devicetree/bindings/spi/mediatek,spi-mtk-snfi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SPI-NAND flash controller for MediaTek ARM SoCs
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maintainers:
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- Chuanhong Guo <gch981213@gmail.com>
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description: |
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The Mediatek SPI-NAND flash controller is an extended version of
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the Mediatek NAND flash controller. It can perform standard SPI
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instructions with one continuous write and one read for up-to 0xa0
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bytes. It also supports typical SPI-NAND page cache operations
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in single, dual or quad IO mode with pipelined ECC encoding/decoding
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using the accompanying ECC engine. There should be only one spi
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slave device following generic spi bindings.
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allOf:
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- $ref: /schemas/spi/spi-controller.yaml#
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properties:
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compatible:
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enum:
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- mediatek,mt7622-snand
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- mediatek,mt7629-snand
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reg:
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items:
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- description: core registers
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interrupts:
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items:
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- description: NFI interrupt
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clocks:
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items:
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- description: clock used for the controller
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- description: clock used for the SPI bus
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clock-names:
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items:
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- const: nfi_clk
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- const: pad_clk
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nand-ecc-engine:
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description: device-tree node of the accompanying ECC engine.
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$ref: /schemas/types.yaml#/definitions/phandle
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- nand-ecc-engine
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7622-clk.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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snfi: spi@1100d000 {
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compatible = "mediatek,mt7622-snand";
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reg = <0 0x1100d000 0 0x1000>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
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clock-names = "nfi_clk", "pad_clk";
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nand-ecc-engine = <&bch>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash@0 {
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compatible = "spi-nand";
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reg = <0>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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nand-ecc-engine = <&snfi>;
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};
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};
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};

‎Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml

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maxItems: 2
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interconnect-names:
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minItems: 1
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items:
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- const: qspi-config
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- const: qspi-memory

‎Documentation/devicetree/bindings/spi/renesas,rspi.yaml

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- enum:
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- renesas,rspi-r7s72100 # RZ/A1H
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- renesas,rspi-r7s9210 # RZ/A2
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- renesas,r9a07g043-rspi # RZ/G2UL
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- renesas,r9a07g044-rspi # RZ/G2{L,LC}
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- renesas,r9a07g054-rspi # RZ/V2L
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- const: renesas,rspi-rz
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contains:
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enum:
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- renesas,qspi
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- renesas,r9a07g043-rspi
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- renesas,r9a07g044-rspi
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- renesas,r9a07g054-rspi
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then:

‎MAINTAINERS

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F: Documentation/devicetree/bindings/mmc/aspeed,sdhci.yaml
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F: drivers/mmc/host/sdhci-of-aspeed*
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ASPEED SMC SPI DRIVER
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M: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
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M: Cédric Le Goater <clg@kaod.org>
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L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)
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L: openbmc@lists.ozlabs.org (moderated for non-subscribers)
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L: linux-spi@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
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F: drivers/spi/spi-aspeed-smc.c
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ASPEED VIDEO ENGINE DRIVER
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M: Eddie James <eajames@linux.ibm.com>
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L: linux-media@vger.kernel.org

‎drivers/mtd/spi-nor/controllers/Kconfig

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# SPDX-License-Identifier: GPL-2.0-only
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config SPI_ASPEED_SMC
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tristate "Aspeed flash controllers in SPI mode"
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depends on ARCH_ASPEED || COMPILE_TEST
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depends on HAS_IOMEM && OF
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help
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This enables support for the Firmware Memory controller (FMC)
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in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips,
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and support for the SPI flash memory controller (SPI) for
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the host firmware. The implementation only supports SPI NOR.
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config SPI_HISI_SFC
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tristate "Hisilicon FMC SPI NOR Flash Controller(SFC)"
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depends on ARCH_HISI || COMPILE_TEST

‎drivers/mtd/spi-nor/controllers/Makefile

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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
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obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
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obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o

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