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ayalevin123Saeed Mahameed
ayalevin123
authored and
Saeed Mahameed
committed
net/mlx5e: Refactor TIR configuration function
Refactor mlx5e_build_indir_tir_ctx_hash for better code re-use. TIR stands for Transport Interface Receive, which is responsible for all transport related operations on the receive side. Added a static array with TIR default configuration values. This separates configuration values from command setting, which is needed for downstream patch. Signed-off-by: Aya Levin <ayal@mellanox.com> Reviewed-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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4 files changed

+87
-104
lines changed

4 files changed

+87
-104
lines changed

‎drivers/net/ethernet/mellanox/mlx5/core/en.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -797,9 +797,10 @@ struct mlx5e_redirect_rqt_param {
797797
int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
798798
struct mlx5e_redirect_rqt_param rrp);
799799
void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
800-
enum mlx5e_traffic_types tt,
800+
const struct mlx5e_tirc_config *ttconfig,
801801
void *tirc, bool inner);
802802
void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen);
803+
struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
803804

804805
int mlx5e_open_locked(struct net_device *netdev);
805806
int mlx5e_close_locked(struct net_device *netdev);

‎drivers/net/ethernet/mellanox/mlx5/core/en/fs.h

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,22 @@ enum mlx5e_traffic_types {
7373
MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
7474
};
7575

76+
struct mlx5e_tirc_config {
77+
u8 l3_prot_type;
78+
u8 l4_prot_type;
79+
u32 rx_hash_fields;
80+
};
81+
82+
#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
83+
MLX5_HASH_FIELD_SEL_DST_IP)
84+
#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
85+
MLX5_HASH_FIELD_SEL_DST_IP |\
86+
MLX5_HASH_FIELD_SEL_L4_SPORT |\
87+
MLX5_HASH_FIELD_SEL_L4_DPORT)
88+
#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
89+
MLX5_HASH_FIELD_SEL_DST_IP |\
90+
MLX5_HASH_FIELD_SEL_IPSEC_SPI)
91+
7692
enum mlx5e_tunnel_types {
7793
MLX5E_TT_IPV4_GRE,
7894
MLX5E_TT_IPV6_GRE,

‎drivers/net/ethernet/mellanox/mlx5/core/en_main.c

Lines changed: 66 additions & 101 deletions
Original file line numberDiff line numberDiff line change
@@ -2607,6 +2607,54 @@ static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
26072607
mlx5e_redirect_rqts(priv, drop_rrp);
26082608
}
26092609

2610+
static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2611+
[MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2612+
.l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2613+
.rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2614+
},
2615+
[MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2616+
.l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2617+
.rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2618+
},
2619+
[MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2620+
.l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2621+
.rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2622+
},
2623+
[MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2624+
.l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2625+
.rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2626+
},
2627+
[MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2628+
.l4_prot_type = 0,
2629+
.rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2630+
},
2631+
[MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2632+
.l4_prot_type = 0,
2633+
.rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2634+
},
2635+
[MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2636+
.l4_prot_type = 0,
2637+
.rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2638+
},
2639+
[MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2640+
.l4_prot_type = 0,
2641+
.rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2642+
},
2643+
[MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2644+
.l4_prot_type = 0,
2645+
.rx_hash_fields = MLX5_HASH_IP,
2646+
},
2647+
[MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2648+
.l4_prot_type = 0,
2649+
.rx_hash_fields = MLX5_HASH_IP,
2650+
},
2651+
};
2652+
2653+
struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2654+
{
2655+
return tirc_default_config[tt];
2656+
}
2657+
26102658
static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
26112659
{
26122660
if (!params->lro_en)
@@ -2623,24 +2671,12 @@ static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
26232671
}
26242672

26252673
void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2626-
enum mlx5e_traffic_types tt,
2674+
const struct mlx5e_tirc_config *ttconfig,
26272675
void *tirc, bool inner)
26282676
{
26292677
void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
26302678
MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
26312679

2632-
#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2633-
MLX5_HASH_FIELD_SEL_DST_IP)
2634-
2635-
#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2636-
MLX5_HASH_FIELD_SEL_DST_IP |\
2637-
MLX5_HASH_FIELD_SEL_L4_SPORT |\
2638-
MLX5_HASH_FIELD_SEL_L4_DPORT)
2639-
2640-
#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2641-
MLX5_HASH_FIELD_SEL_DST_IP |\
2642-
MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2643-
26442680
MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
26452681
if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
26462682
void *rss_key = MLX5_ADDR_OF(tirc, tirc,
@@ -2651,88 +2687,12 @@ void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
26512687
MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
26522688
memcpy(rss_key, params->toeplitz_hash_key, len);
26532689
}
2654-
2655-
switch (tt) {
2656-
case MLX5E_TT_IPV4_TCP:
2657-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2658-
MLX5_L3_PROT_TYPE_IPV4);
2659-
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2660-
MLX5_L4_PROT_TYPE_TCP);
2661-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2662-
MLX5_HASH_IP_L4PORTS);
2663-
break;
2664-
2665-
case MLX5E_TT_IPV6_TCP:
2666-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2667-
MLX5_L3_PROT_TYPE_IPV6);
2668-
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2669-
MLX5_L4_PROT_TYPE_TCP);
2670-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2671-
MLX5_HASH_IP_L4PORTS);
2672-
break;
2673-
2674-
case MLX5E_TT_IPV4_UDP:
2675-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2676-
MLX5_L3_PROT_TYPE_IPV4);
2677-
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2678-
MLX5_L4_PROT_TYPE_UDP);
2679-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2680-
MLX5_HASH_IP_L4PORTS);
2681-
break;
2682-
2683-
case MLX5E_TT_IPV6_UDP:
2684-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2685-
MLX5_L3_PROT_TYPE_IPV6);
2686-
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2687-
MLX5_L4_PROT_TYPE_UDP);
2688-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2689-
MLX5_HASH_IP_L4PORTS);
2690-
break;
2691-
2692-
case MLX5E_TT_IPV4_IPSEC_AH:
2693-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2694-
MLX5_L3_PROT_TYPE_IPV4);
2695-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2696-
MLX5_HASH_IP_IPSEC_SPI);
2697-
break;
2698-
2699-
case MLX5E_TT_IPV6_IPSEC_AH:
2700-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2701-
MLX5_L3_PROT_TYPE_IPV6);
2702-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2703-
MLX5_HASH_IP_IPSEC_SPI);
2704-
break;
2705-
2706-
case MLX5E_TT_IPV4_IPSEC_ESP:
2707-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2708-
MLX5_L3_PROT_TYPE_IPV4);
2709-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2710-
MLX5_HASH_IP_IPSEC_SPI);
2711-
break;
2712-
2713-
case MLX5E_TT_IPV6_IPSEC_ESP:
2714-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2715-
MLX5_L3_PROT_TYPE_IPV6);
2716-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2717-
MLX5_HASH_IP_IPSEC_SPI);
2718-
break;
2719-
2720-
case MLX5E_TT_IPV4:
2721-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2722-
MLX5_L3_PROT_TYPE_IPV4);
2723-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2724-
MLX5_HASH_IP);
2725-
break;
2726-
2727-
case MLX5E_TT_IPV6:
2728-
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2729-
MLX5_L3_PROT_TYPE_IPV6);
2730-
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2731-
MLX5_HASH_IP);
2732-
break;
2733-
default:
2734-
WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2735-
}
2690+
MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2691+
ttconfig->l3_prot_type);
2692+
MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2693+
ttconfig->l4_prot_type);
2694+
MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2695+
ttconfig->rx_hash_fields);
27362696
}
27372697

27382698
void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
@@ -2746,8 +2706,9 @@ void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
27462706

27472707
for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
27482708
memset(tirc, 0, ctxlen);
2749-
mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc,
2750-
false);
2709+
mlx5e_build_indir_tir_ctx_hash(&priv->channels.params,
2710+
&tirc_default_config[tt],
2711+
tirc, false);
27512712
mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
27522713
}
27532714

@@ -2756,8 +2717,9 @@ void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
27562717

27572718
for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
27582719
memset(tirc, 0, ctxlen);
2759-
mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc,
2760-
true);
2720+
mlx5e_build_indir_tir_ctx_hash(&priv->channels.params,
2721+
&tirc_default_config[tt],
2722+
tirc, true);
27612723
mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
27622724
inlen);
27632725
}
@@ -2816,7 +2778,8 @@ static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
28162778
MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
28172779
MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
28182780

2819-
mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2781+
mlx5e_build_indir_tir_ctx_hash(&priv->channels.params,
2782+
&tirc_default_config[tt], tirc, true);
28202783
}
28212784

28222785
static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
@@ -3208,7 +3171,9 @@ static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
32083171

32093172
MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
32103173
MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3211-
mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
3174+
3175+
mlx5e_build_indir_tir_ctx_hash(&priv->channels.params,
3176+
&tirc_default_config[tt], tirc, false);
32123177
}
32133178

32143179
static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)

‎drivers/net/ethernet/mellanox/mlx5/core/en_tc.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -360,14 +360,15 @@ static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
360360
void *tirc;
361361

362362
for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
363+
struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
364+
363365
memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
364366
tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
365367

366368
MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
367369
MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
368370
MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
369-
mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
370-
371+
mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, &ttconfig, tirc, false);
371372
err = mlx5_core_create_tir(hp->func_mdev, in,
372373
MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
373374
if (err) {

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