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Commit d96801b

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author
Uwe Kleine-König
committed
ARM: imx: remove deprecated symbols as all users are gone now
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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7 files changed

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‎arch/arm/plat-mxc/include/mach/mx1.h

Lines changed: 0 additions & 127 deletions
Original file line numberDiff line numberDiff line change
@@ -165,131 +165,4 @@
165165
*/
166166
#define USBD_INT0 MX1_USBD_INT0
167167

168-
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
169-
/* these should go away */
170-
#define IMX_IO_PHYS MX1_IO_BASE_ADDR
171-
#define IMX_IO_SIZE MX1_IO_SIZE
172-
#define IMX_CS0_PHYS MX1_CS0_PHYS
173-
#define IMX_CS0_SIZE MX1_CS0_SIZE
174-
#define IMX_CS1_PHYS MX1_CS1_PHYS
175-
#define IMX_CS1_SIZE MX1_CS1_SIZE
176-
#define IMX_CS2_PHYS MX1_CS2_PHYS
177-
#define IMX_CS2_SIZE MX1_CS2_SIZE
178-
#define IMX_CS3_PHYS MX1_CS3_PHYS
179-
#define IMX_CS3_SIZE MX1_CS3_SIZE
180-
#define IMX_CS4_PHYS MX1_CS4_PHYS
181-
#define IMX_CS4_SIZE MX1_CS4_SIZE
182-
#define IMX_CS5_PHYS MX1_CS5_PHYS
183-
#define IMX_CS5_SIZE MX1_CS5_SIZE
184-
#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR
185-
#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR
186-
#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR
187-
#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR
188-
#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR
189-
#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR
190-
#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR
191-
#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR
192-
#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR
193-
#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR
194-
#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR
195-
#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR
196-
#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR
197-
#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR
198-
#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR
199-
#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR
200-
#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR
201-
#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR
202-
#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR
203-
#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR
204-
#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR
205-
#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR
206-
#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR
207-
#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR
208-
#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR
209-
#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR
210-
#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR
211-
#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR
212-
#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR
213-
#define IO_ADDRESS(x) MX1_IO_ADDRESS(x)
214-
#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
215-
#define INT_SOFTINT MX1_INT_SOFTINT
216-
#define CSI_INT MX1_CSI_INT
217-
#define DSPA_MAC_INT MX1_DSPA_MAC_INT
218-
#define DSPA_INT MX1_DSPA_INT
219-
#define COMP_INT MX1_COMP_INT
220-
#define MSHC_XINT MX1_MSHC_XINT
221-
#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA
222-
#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB
223-
#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC
224-
#define LCDC_INT MX1_LCDC_INT
225-
#define SIM_INT MX1_SIM_INT
226-
#define SIM_DATA_INT MX1_SIM_DATA_INT
227-
#define RTC_INT MX1_RTC_INT
228-
#define RTC_SAMINT MX1_RTC_SAMINT
229-
#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR
230-
#define UART2_MINT_RTS MX1_UART2_MINT_RTS
231-
#define UART2_MINT_DTR MX1_UART2_MINT_DTR
232-
#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC
233-
#define UART2_MINT_TX MX1_UART2_MINT_TX
234-
#define UART2_MINT_RX MX1_UART2_MINT_RX
235-
#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR
236-
#define UART1_MINT_RTS MX1_UART1_MINT_RTS
237-
#define UART1_MINT_DTR MX1_UART1_MINT_DTR
238-
#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC
239-
#define UART1_MINT_TX MX1_UART1_MINT_TX
240-
#define UART1_MINT_RX MX1_UART1_MINT_RX
241-
#define VOICE_DAC_INT MX1_VOICE_DAC_INT
242-
#define VOICE_ADC_INT MX1_VOICE_ADC_INT
243-
#define PEN_DATA_INT MX1_PEN_DATA_INT
244-
#define PWM_INT MX1_PWM_INT
245-
#define SDHC_INT MX1_SDHC_INT
246-
#define I2C_INT MX1_INT_I2C
247-
#define CSPI_INT MX1_CSPI_INT
248-
#define SSI_TX_INT MX1_SSI_TX_INT
249-
#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
250-
#define SSI_RX_INT MX1_SSI_RX_INT
251-
#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT
252-
#define TOUCH_INT MX1_TOUCH_INT
253-
#define USBD_INT1 MX1_USBD_INT1
254-
#define USBD_INT2 MX1_USBD_INT2
255-
#define USBD_INT3 MX1_USBD_INT3
256-
#define USBD_INT4 MX1_USBD_INT4
257-
#define USBD_INT5 MX1_USBD_INT5
258-
#define USBD_INT6 MX1_USBD_INT6
259-
#define BTSYS_INT MX1_BTSYS_INT
260-
#define BTTIM_INT MX1_BTTIM_INT
261-
#define BTWUI_INT MX1_BTWUI_INT
262-
#define TIM2_INT MX1_TIM2_INT
263-
#define TIM1_INT MX1_TIM1_INT
264-
#define DMA_ERR MX1_DMA_ERR
265-
#define DMA_INT MX1_DMA_INT
266-
#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD
267-
#define WDT_INT MX1_WDT_INT
268-
#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T
269-
#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R
270-
#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T
271-
#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R
272-
#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT
273-
#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R
274-
#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC
275-
#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT
276-
#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN
277-
#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC
278-
#define DMA_REQ_EXT MX1_DMA_REQ_EXT
279-
#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC
280-
#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R
281-
#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T
282-
#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T
283-
#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R
284-
#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC
285-
#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC
286-
#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x)
287-
#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R
288-
#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T
289-
#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T
290-
#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R
291-
#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T
292-
#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R
293-
#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */
294-
295168
#endif /* ifndef __MACH_MX1_H__ */

‎arch/arm/plat-mxc/include/mach/mx21.h

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -179,38 +179,4 @@
179179
#define MX21_DMA_REQ_CSI_STAT 30
180180
#define MX21_DMA_REQ_CSI_RX 31
181181

182-
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
183-
/* these should go away */
184-
#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
185-
#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
186-
#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
187-
#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
188-
#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
189-
#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
190-
#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
191-
#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
192-
#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
193-
#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
194-
#define X_MEMC_SIZE MX21_X_MEMC_SIZE
195-
#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
196-
#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
197-
#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
198-
#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
199-
#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
200-
#define MXC_INT_FIRI MX21_INT_FIRI
201-
#define MXC_INT_BMI MX21_INT_BMI
202-
#define MXC_INT_EMMAENC MX21_INT_EMMAENC
203-
#define MXC_INT_EMMADEC MX21_INT_EMMADEC
204-
#define MXC_INT_USBWKUP MX21_INT_USBWKUP
205-
#define MXC_INT_USBDMA MX21_INT_USBDMA
206-
#define MXC_INT_USBHOST MX21_INT_USBHOST
207-
#define MXC_INT_USBFUNC MX21_INT_USBFUNC
208-
#define MXC_INT_USBMNP MX21_INT_USBMNP
209-
#define MXC_INT_USBCTRL MX21_INT_USBCTRL
210-
#define MXC_INT_USBCTRL MX21_INT_USBCTRL
211-
#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
212-
#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
213-
#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
214-
#endif
215-
216182
#endif /* ifndef __MACH_MX21_H__ */

‎arch/arm/plat-mxc/include/mach/mx27.h

Lines changed: 0 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -244,73 +244,4 @@ static inline void mx27_setup_weimcs(size_t cs,
244244
extern int mx27_revision(void);
245245
#endif
246246

247-
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
248-
/* these should go away */
249-
#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
250-
#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
251-
#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
252-
#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
253-
#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
254-
#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
255-
#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
256-
#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
257-
#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
258-
#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
259-
#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
260-
#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
261-
#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
262-
#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
263-
#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
264-
#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
265-
#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
266-
#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
267-
#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
268-
#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
269-
#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
270-
#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
271-
#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
272-
#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
273-
#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
274-
#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
275-
#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
276-
#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
277-
#define X_MEMC_SIZE MX27_X_MEMC_SIZE
278-
#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
279-
#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
280-
#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
281-
#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
282-
#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
283-
#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
284-
#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
285-
#define MXC_INT_I2C2 MX27_INT_I2C2
286-
#define MXC_INT_GPT6 MX27_INT_GPT6
287-
#define MXC_INT_GPT5 MX27_INT_GPT5
288-
#define MXC_INT_GPT4 MX27_INT_GPT4
289-
#define MXC_INT_RTIC MX27_INT_RTIC
290-
#define MXC_INT_SDHC MX27_INT_SDHC
291-
#define MXC_INT_SDHC3 MX27_INT_SDHC3
292-
#define MXC_INT_ATA MX27_INT_ATA
293-
#define MXC_INT_UART6 MX27_INT_UART6
294-
#define MXC_INT_UART5 MX27_INT_UART5
295-
#define MXC_INT_FEC MX27_INT_FEC
296-
#define MXC_INT_VPU MX27_INT_VPU
297-
#define MXC_INT_USB1 MX27_INT_USB1
298-
#define MXC_INT_USB2 MX27_INT_USB2
299-
#define MXC_INT_USB3 MX27_INT_USB3
300-
#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
301-
#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
302-
#define MXC_INT_SAHARA MX27_INT_SAHARA
303-
#define MXC_INT_IIM MX27_INT_IIM
304-
#define MXC_INT_CCM MX27_INT_CCM
305-
#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
306-
#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
307-
#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
308-
#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
309-
#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
310-
#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
311-
#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
312-
#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
313-
#define DMA_REQ_NFC MX27_DMA_REQ_NFC
314-
#endif
315-
316247
#endif /* ifndef __MACH_MX27_H__ */

‎arch/arm/plat-mxc/include/mach/mx2x.h

Lines changed: 0 additions & 112 deletions
Original file line numberDiff line numberDiff line change
@@ -141,116 +141,4 @@
141141
#define MX2x_DMA_REQ_CSI_STAT 30
142142
#define MX2x_DMA_REQ_CSI_RX 31
143143

144-
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
145-
/* these should go away */
146-
#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
147-
#define AIPI_SIZE MX2x_AIPI_SIZE
148-
#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
149-
#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
150-
#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
151-
#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
152-
#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
153-
#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
154-
#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
155-
#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
156-
#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
157-
#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
158-
#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
159-
#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
160-
#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
161-
#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
162-
#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
163-
#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
164-
#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
165-
#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
166-
#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
167-
#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
168-
#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
169-
#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
170-
#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
171-
#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
172-
#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
173-
#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
174-
#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
175-
#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
176-
#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
177-
#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
178-
#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
179-
#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
180-
#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
181-
#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
182-
#define SAHB1_SIZE MX2x_SAHB1_SIZE
183-
#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
184-
#define MXC_INT_CSPI3 MX2x_INT_CSPI3
185-
#define MXC_INT_GPIO MX2x_INT_GPIO
186-
#define MXC_INT_SDHC2 MX2x_INT_SDHC2
187-
#define MXC_INT_SDHC1 MX2x_INT_SDHC1
188-
#define MXC_INT_I2C MX2x_INT_I2C
189-
#define MXC_INT_SSI2 MX2x_INT_SSI2
190-
#define MXC_INT_SSI1 MX2x_INT_SSI1
191-
#define MXC_INT_CSPI2 MX2x_INT_CSPI2
192-
#define MXC_INT_CSPI1 MX2x_INT_CSPI1
193-
#define MXC_INT_UART4 MX2x_INT_UART4
194-
#define MXC_INT_UART3 MX2x_INT_UART3
195-
#define MXC_INT_UART2 MX2x_INT_UART2
196-
#define MXC_INT_UART1 MX2x_INT_UART1
197-
#define MXC_INT_KPP MX2x_INT_KPP
198-
#define MXC_INT_RTC MX2x_INT_RTC
199-
#define MXC_INT_PWM MX2x_INT_PWM
200-
#define MXC_INT_GPT3 MX2x_INT_GPT3
201-
#define MXC_INT_GPT2 MX2x_INT_GPT2
202-
#define MXC_INT_GPT1 MX2x_INT_GPT1
203-
#define MXC_INT_WDOG MX2x_INT_WDOG
204-
#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
205-
#define MXC_INT_NANDFC MX2x_INT_NANDFC
206-
#define MXC_INT_CSI MX2x_INT_CSI
207-
#define MXC_INT_DMACH0 MX2x_INT_DMACH0
208-
#define MXC_INT_DMACH1 MX2x_INT_DMACH1
209-
#define MXC_INT_DMACH2 MX2x_INT_DMACH2
210-
#define MXC_INT_DMACH3 MX2x_INT_DMACH3
211-
#define MXC_INT_DMACH4 MX2x_INT_DMACH4
212-
#define MXC_INT_DMACH5 MX2x_INT_DMACH5
213-
#define MXC_INT_DMACH6 MX2x_INT_DMACH6
214-
#define MXC_INT_DMACH7 MX2x_INT_DMACH7
215-
#define MXC_INT_DMACH8 MX2x_INT_DMACH8
216-
#define MXC_INT_DMACH9 MX2x_INT_DMACH9
217-
#define MXC_INT_DMACH10 MX2x_INT_DMACH10
218-
#define MXC_INT_DMACH11 MX2x_INT_DMACH11
219-
#define MXC_INT_DMACH12 MX2x_INT_DMACH12
220-
#define MXC_INT_DMACH13 MX2x_INT_DMACH13
221-
#define MXC_INT_DMACH14 MX2x_INT_DMACH14
222-
#define MXC_INT_DMACH15 MX2x_INT_DMACH15
223-
#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
224-
#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
225-
#define MXC_INT_SLCDC MX2x_INT_SLCDC
226-
#define MXC_INT_LCDC MX2x_INT_LCDC
227-
#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
228-
#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
229-
#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
230-
#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
231-
#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
232-
#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
233-
#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
234-
#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
235-
#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
236-
#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
237-
#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
238-
#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
239-
#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
240-
#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
241-
#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
242-
#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
243-
#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
244-
#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
245-
#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
246-
#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
247-
#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
248-
#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
249-
#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
250-
#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
251-
#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
252-
#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
253-
#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
254-
#endif
255-
256144
#endif /* ifndef __MACH_MX2x_H__ */

‎arch/arm/plat-mxc/include/mach/mx31.h

Lines changed: 0 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -215,36 +215,4 @@ static inline void mx31_setup_weimcs(size_t cs,
215215
#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
216216
#define MX31_SYSTEM_REV_NUM 3
217217

218-
#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
219-
/* these should go away */
220-
#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
221-
#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
222-
#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
223-
#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
224-
#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
225-
#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
226-
#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
227-
#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
228-
#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
229-
#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
230-
#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
231-
#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
232-
#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
233-
#define MXC_INT_FIRI MX31_INT_FIRI
234-
#define MXC_INT_MBX MX31_INT_MBX
235-
#define MXC_INT_CSPI3 MX31_INT_CSPI3
236-
#define MXC_INT_SIM2 MX31_INT_SIM2
237-
#define MXC_INT_SIM1 MX31_INT_SIM1
238-
#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
239-
#define MXC_INT_USB1 MX31_INT_USB1
240-
#define MXC_INT_USB2 MX31_INT_USB2
241-
#define MXC_INT_USB3 MX31_INT_USB3
242-
#define MXC_INT_USB4 MX31_INT_USB4
243-
#define MXC_INT_MSHC2 MX31_INT_MSHC2
244-
#define MXC_INT_UART4 MX31_INT_UART4
245-
#define MXC_INT_UART5 MX31_INT_UART5
246-
#define MXC_INT_CCM MX31_INT_CCM
247-
#define MXC_INT_PCMCIA MX31_INT_PCMCIA
248-
#endif
249-
250218
#endif /* ifndef __MACH_MX31_H__ */

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