drm/i915/skl: Correcting the flushing of pipe

Sonika Jindal · danvet · commit d9d8e6b3c013 · 2014-12-15T11:25:29.000+01:00
We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.

Signed-off-by: Sonika Jindal &lt;sonika.jindal@intel.com&gt;
Reviewed-by: Tvrtko Ursulin &lt;tvrtko.ursulin@intel.com&gt;
Reviewed-by: Satheeshakrishna M&lt;satheeshakrishna.m@intel.com&gt;
Signed-off-by: Daniel Vetter &lt;daniel.vetter@ffwll.ch&gt;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
@@ -3004,9 +3004,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
 		    skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
 			skl_wm_flush_pipe(dev_priv, pipe, 2);
 			intel_wait_for_vblank(dev, pipe);
+			reallocated[pipe] = true;
 		}
-
-		reallocated[pipe] = true;
 	}
 
 	/*

Original file line number	Diff line number	Diff line change
`@@ -3004,9 +3004,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,`
`3004`	`3004`	`skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {`
`3005`	`3005`	`skl_wm_flush_pipe(dev_priv, pipe, 2);`
`3006`	`3006`	`intel_wait_for_vblank(dev, pipe);`
	`3007`	`+ reallocated[pipe] = true;`
`3007`	`3008`	`}`
`3008`		`-`
`3009`		`- reallocated[pipe] = true;`
`3010`	`3009`	`}`
`3011`	`3010`
`3012`	`3011`	`/*`