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ludovicbarreMarc Zyngier
ludovicbarre
authored and
Marc Zyngier
committed
irqchip/stm32: Add suspend support
This patch adds suspend feature. -Use default irq_set_wake function to store wakeup request. -Suspend function set wake_active into imr of each bank and save rising/falling trigger registers. -Resume function restore the mask_cache interrupt into imr of each bank and restore rising/falling trigger registers. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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‎drivers/irqchip/irq-stm32-exti.c

Lines changed: 52 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,14 @@ struct stm32_exti_bank {
2929

3030
#define UNDEF_REG ~0
3131

32+
struct stm32_exti_chip_data {
33+
const struct stm32_exti_bank *reg_bank;
34+
u32 rtsr_cache;
35+
u32 ftsr_cache;
36+
};
37+
38+
static struct stm32_exti_chip_data *stm32_exti_data;
39+
3240
static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
3341
.imr_ofst = 0x00,
3442
.emr_ofst = 0x04,
@@ -81,7 +89,8 @@ static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
8189

8290
static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
8391
{
84-
const struct stm32_exti_bank *stm32_bank = gc->private;
92+
struct stm32_exti_chip_data *chip_data = gc->private;
93+
const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
8594
unsigned long pending;
8695

8796
pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
@@ -119,7 +128,8 @@ static void stm32_irq_handler(struct irq_desc *desc)
119128
static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
120129
{
121130
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
122-
const struct stm32_exti_bank *stm32_bank = gc->private;
131+
struct stm32_exti_chip_data *chip_data = gc->private;
132+
const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
123133
int pin = data->hwirq % IRQS_PER_BANK;
124134
u32 rtsr, ftsr;
125135

@@ -154,25 +164,36 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
154164
return 0;
155165
}
156166

157-
static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
167+
static void stm32_irq_suspend(struct irq_chip_generic *gc)
158168
{
159-
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
160-
const struct stm32_exti_bank *stm32_bank = gc->private;
161-
int pin = data->hwirq % IRQS_PER_BANK;
162-
u32 imr;
169+
struct stm32_exti_chip_data *chip_data = gc->private;
170+
const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
163171

164172
irq_gc_lock(gc);
165173

166-
imr = irq_reg_readl(gc, stm32_bank->imr_ofst);
167-
if (on)
168-
imr |= BIT(pin);
169-
else
170-
imr &= ~BIT(pin);
171-
irq_reg_writel(gc, imr, stm32_bank->imr_ofst);
174+
/* save rtsr, ftsr registers */
175+
chip_data->rtsr_cache = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
176+
chip_data->ftsr_cache = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
177+
178+
irq_reg_writel(gc, gc->wake_active, stm32_bank->imr_ofst);
172179

173180
irq_gc_unlock(gc);
181+
}
174182

175-
return 0;
183+
static void stm32_irq_resume(struct irq_chip_generic *gc)
184+
{
185+
struct stm32_exti_chip_data *chip_data = gc->private;
186+
const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
187+
188+
irq_gc_lock(gc);
189+
190+
/* restore rtsr, ftsr registers */
191+
irq_reg_writel(gc, chip_data->rtsr_cache, stm32_bank->rtsr_ofst);
192+
irq_reg_writel(gc, chip_data->ftsr_cache, stm32_bank->ftsr_ofst);
193+
194+
irq_reg_writel(gc, gc->mask_cache, stm32_bank->imr_ofst);
195+
196+
irq_gc_unlock(gc);
176197
}
177198

178199
static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
@@ -205,7 +226,8 @@ static const struct irq_domain_ops irq_exti_domain_ops = {
205226
static void stm32_irq_ack(struct irq_data *d)
206227
{
207228
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
208-
const struct stm32_exti_bank *stm32_bank = gc->private;
229+
struct stm32_exti_chip_data *chip_data = gc->private;
230+
const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
209231

210232
irq_gc_lock(gc);
211233

@@ -232,6 +254,11 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
232254
return -ENOMEM;
233255
}
234256

257+
stm32_exti_data = kcalloc(bank_nr, sizeof(*stm32_exti_data),
258+
GFP_KERNEL);
259+
if (!stm32_exti_data)
260+
return -ENOMEM;
261+
235262
domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK,
236263
&irq_exti_domain_ops, NULL);
237264
if (!domain) {
@@ -251,8 +278,11 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
251278

252279
for (i = 0; i < bank_nr; i++) {
253280
const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
281+
struct stm32_exti_chip_data *chip_data = &stm32_exti_data[i];
254282
u32 irqs_mask;
255283

284+
chip_data->reg_bank = stm32_bank;
285+
256286
gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
257287

258288
gc->reg_base = base;
@@ -261,9 +291,13 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
261291
gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
262292
gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
263293
gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
264-
gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
294+
gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
295+
gc->suspend = stm32_irq_suspend;
296+
gc->resume = stm32_irq_resume;
297+
gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
298+
265299
gc->chip_types->regs.mask = stm32_bank->imr_ofst;
266-
gc->private = (void *)stm32_bank;
300+
gc->private = (void *)chip_data;
267301

268302
/* Determine number of irqs supported */
269303
writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
@@ -300,6 +334,7 @@ __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
300334
irq_domain_remove(domain);
301335
out_unmap:
302336
iounmap(base);
337+
kfree(stm32_exti_data);
303338
return ret;
304339
}
305340

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