Skip to content

Commit db7e9f7

Browse files
davem330davem330
committed
Merge branch '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next-queue
Jeff Kirsher says: ==================== 40GbE Intel Wired LAN Driver Updates 2016-12-02 This series contains updates to i40e and i40evf only. Alex provides changes so that we are much more robust about defining what we can and cannot offload in i40e and i40evf by doing additional checks other than L4 tunnel header length. Jake provides several fixes/changes, first cleaning up a label that is unnecessary, as well as cleaned up the use of a "magic number". Clarified the code by separating the global private flags and the regular private flags per interface into two arrays, so that future additions will not produce duplication and buggy code. Adds additional checks to protect against NULL values for msix_entries and q_vectors pointers. Michal adds Clause22 method for accessing registers for some external PHYs. Piotr adds additional protocol support for the admin queue discover capabilities function. Tushar Dave fixes a panic seen on SPARC, where writel() should not be used to write directly to a memory address but only to a memory mapped I/O address otherwise it causes data access exceptions. Joe Perches separates out a section of code into its own function, to help reduce i40evf_reset_task() a bit. Alan fixes an issue by checking for NULL before dereferencing msix_entries and returning early in the case where it is NULL within the i40evf_close() code path. Henry provides code cleanup to remove unreachable and redundant sections of code. Fixed up an issue where new NICs were not identifying "unknown PHYs" correctly. Harshitha fixes a issue where the ethtool "Supported Link" modes list backplane interfaces on X722 devices for 10 GbE with SFP+ and Cortina retimer, where these interfaces should not be visible to the user since they cannot use them. Carolyn changes an X722 informational message so that it only appears when extra messages are desired. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
2 parents 2bb1487 + 23bb6dc commit db7e9f7

File tree

9 files changed

+511
-184
lines changed

9 files changed

+511
-184
lines changed

‎drivers/net/ethernet/intel/i40e/i40e.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -359,6 +359,7 @@ struct i40e_pf {
359359
#define I40E_FLAG_HAVE_10GBASET_PHY BIT_ULL(48)
360360
#define I40E_FLAG_PF_MAC BIT_ULL(50)
361361
#define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT_ULL(51)
362+
#define I40E_FLAG_HAVE_CRT_RETIMER BIT_ULL(52)
362363

363364
/* tracks features that get auto disabled by errors */
364365
u64 auto_disable_flags;

‎drivers/net/ethernet/intel/i40e/i40e_common.c

Lines changed: 174 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1854,7 +1854,8 @@ i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
18541854
else
18551855
hw_link_info->lse_enable = false;
18561856

1857-
if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1857+
if ((hw->mac.type == I40E_MAC_XL710) &&
1858+
(hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
18581859
hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
18591860
hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
18601861

@@ -2168,6 +2169,40 @@ enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
21682169
return status;
21692170
}
21702171

2172+
/**
2173+
* i40e_aq_set_vsi_bc_promisc_on_vlan
2174+
* @hw: pointer to the hw struct
2175+
* @seid: vsi number
2176+
* @enable: set broadcast promiscuous enable/disable for a given VLAN
2177+
* @vid: The VLAN tag filter - capture any broadcast packet with this VLAN tag
2178+
* @cmd_details: pointer to command details structure or NULL
2179+
**/
2180+
i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2181+
u16 seid, bool enable, u16 vid,
2182+
struct i40e_asq_cmd_details *cmd_details)
2183+
{
2184+
struct i40e_aq_desc desc;
2185+
struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2186+
(struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2187+
i40e_status status;
2188+
u16 flags = 0;
2189+
2190+
i40e_fill_default_direct_cmd_desc(&desc,
2191+
i40e_aqc_opc_set_vsi_promiscuous_modes);
2192+
2193+
if (enable)
2194+
flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2195+
2196+
cmd->promiscuous_flags = cpu_to_le16(flags);
2197+
cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2198+
cmd->seid = cpu_to_le16(seid);
2199+
cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2200+
2201+
status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2202+
2203+
return status;
2204+
}
2205+
21712206
/**
21722207
* i40e_aq_set_vsi_broadcast
21732208
* @hw: pointer to the hw struct
@@ -3147,6 +3182,14 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
31473182
break;
31483183
case I40E_AQ_CAP_ID_MNG_MODE:
31493184
p->management_mode = number;
3185+
if (major_rev > 1) {
3186+
p->mng_protocols_over_mctp = logical_id;
3187+
i40e_debug(hw, I40E_DEBUG_INIT,
3188+
"HW Capability: Protocols over MCTP = %d\n",
3189+
p->mng_protocols_over_mctp);
3190+
} else {
3191+
p->mng_protocols_over_mctp = 0;
3192+
}
31503193
break;
31513194
case I40E_AQ_CAP_ID_NPAR_ACTIVE:
31523195
p->npar_enable = number;
@@ -4396,7 +4439,92 @@ i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
43964439
}
43974440

43984441
/**
4399-
* i40e_read_phy_register
4442+
* i40e_read_phy_register_clause22
4443+
* @hw: pointer to the HW structure
4444+
* @reg: register address in the page
4445+
* @phy_adr: PHY address on MDIO interface
4446+
* @value: PHY register value
4447+
*
4448+
* Reads specified PHY register value
4449+
**/
4450+
i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4451+
u16 reg, u8 phy_addr, u16 *value)
4452+
{
4453+
i40e_status status = I40E_ERR_TIMEOUT;
4454+
u8 port_num = (u8)hw->func_caps.mdio_port_num;
4455+
u32 command = 0;
4456+
u16 retry = 1000;
4457+
4458+
command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4459+
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4460+
(I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4461+
(I40E_MDIO_CLAUSE22_STCODE_MASK) |
4462+
(I40E_GLGEN_MSCA_MDICMD_MASK);
4463+
wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4464+
do {
4465+
command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4466+
if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4467+
status = 0;
4468+
break;
4469+
}
4470+
udelay(10);
4471+
retry--;
4472+
} while (retry);
4473+
4474+
if (status) {
4475+
i40e_debug(hw, I40E_DEBUG_PHY,
4476+
"PHY: Can't write command to external PHY.\n");
4477+
} else {
4478+
command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4479+
*value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4480+
I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4481+
}
4482+
4483+
return status;
4484+
}
4485+
4486+
/**
4487+
* i40e_write_phy_register_clause22
4488+
* @hw: pointer to the HW structure
4489+
* @reg: register address in the page
4490+
* @phy_adr: PHY address on MDIO interface
4491+
* @value: PHY register value
4492+
*
4493+
* Writes specified PHY register value
4494+
**/
4495+
i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4496+
u16 reg, u8 phy_addr, u16 value)
4497+
{
4498+
i40e_status status = I40E_ERR_TIMEOUT;
4499+
u8 port_num = (u8)hw->func_caps.mdio_port_num;
4500+
u32 command = 0;
4501+
u16 retry = 1000;
4502+
4503+
command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4504+
wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4505+
4506+
command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4507+
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4508+
(I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4509+
(I40E_MDIO_CLAUSE22_STCODE_MASK) |
4510+
(I40E_GLGEN_MSCA_MDICMD_MASK);
4511+
4512+
wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4513+
do {
4514+
command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4515+
if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4516+
status = 0;
4517+
break;
4518+
}
4519+
udelay(10);
4520+
retry--;
4521+
} while (retry);
4522+
4523+
return status;
4524+
}
4525+
4526+
/**
4527+
* i40e_read_phy_register_clause45
44004528
* @hw: pointer to the HW structure
44014529
* @page: registers page number
44024530
* @reg: register address in the page
@@ -4405,9 +4533,8 @@ i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
44054533
*
44064534
* Reads specified PHY register value
44074535
**/
4408-
i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4409-
u8 page, u16 reg, u8 phy_addr,
4410-
u16 *value)
4536+
i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4537+
u8 page, u16 reg, u8 phy_addr, u16 *value)
44114538
{
44124539
i40e_status status = I40E_ERR_TIMEOUT;
44134540
u32 command = 0;
@@ -4417,8 +4544,8 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,
44174544
command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
44184545
(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
44194546
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4420-
(I40E_MDIO_OPCODE_ADDRESS) |
4421-
(I40E_MDIO_STCODE) |
4547+
(I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4548+
(I40E_MDIO_CLAUSE45_STCODE_MASK) |
44224549
(I40E_GLGEN_MSCA_MDICMD_MASK) |
44234550
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
44244551
wr32(hw, I40E_GLGEN_MSCA(port_num), command);
@@ -4440,8 +4567,8 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,
44404567

44414568
command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
44424569
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4443-
(I40E_MDIO_OPCODE_READ) |
4444-
(I40E_MDIO_STCODE) |
4570+
(I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4571+
(I40E_MDIO_CLAUSE45_STCODE_MASK) |
44454572
(I40E_GLGEN_MSCA_MDICMD_MASK) |
44464573
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
44474574
status = I40E_ERR_TIMEOUT;
@@ -4471,7 +4598,7 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,
44714598
}
44724599

44734600
/**
4474-
* i40e_write_phy_register
4601+
* i40e_write_phy_register_clause45
44754602
* @hw: pointer to the HW structure
44764603
* @page: registers page number
44774604
* @reg: register address in the page
@@ -4480,9 +4607,8 @@ i40e_status i40e_read_phy_register(struct i40e_hw *hw,
44804607
*
44814608
* Writes value to specified PHY register
44824609
**/
4483-
i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4484-
u8 page, u16 reg, u8 phy_addr,
4485-
u16 value)
4610+
i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4611+
u8 page, u16 reg, u8 phy_addr, u16 value)
44864612
{
44874613
i40e_status status = I40E_ERR_TIMEOUT;
44884614
u32 command = 0;
@@ -4492,8 +4618,8 @@ i40e_status i40e_write_phy_register(struct i40e_hw *hw,
44924618
command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
44934619
(page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
44944620
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4495-
(I40E_MDIO_OPCODE_ADDRESS) |
4496-
(I40E_MDIO_STCODE) |
4621+
(I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4622+
(I40E_MDIO_CLAUSE45_STCODE_MASK) |
44974623
(I40E_GLGEN_MSCA_MDICMD_MASK) |
44984624
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
44994625
wr32(hw, I40E_GLGEN_MSCA(port_num), command);
@@ -4517,8 +4643,8 @@ i40e_status i40e_write_phy_register(struct i40e_hw *hw,
45174643

45184644
command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
45194645
(phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4520-
(I40E_MDIO_OPCODE_WRITE) |
4521-
(I40E_MDIO_STCODE) |
4646+
(I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4647+
(I40E_MDIO_CLAUSE45_STCODE_MASK) |
45224648
(I40E_GLGEN_MSCA_MDICMD_MASK) |
45234649
(I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
45244650
status = I40E_ERR_TIMEOUT;
@@ -4580,14 +4706,16 @@ i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
45804706

45814707
for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
45824708
led_addr++) {
4583-
status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4584-
led_addr, phy_addr, &led_reg);
4709+
status = i40e_read_phy_register_clause45(hw,
4710+
I40E_PHY_COM_REG_PAGE,
4711+
led_addr, phy_addr,
4712+
&led_reg);
45854713
if (status)
45864714
goto phy_blinking_end;
45874715
led_ctl = led_reg;
45884716
if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
45894717
led_reg = 0;
4590-
status = i40e_write_phy_register(hw,
4718+
status = i40e_write_phy_register_clause45(hw,
45914719
I40E_PHY_COM_REG_PAGE,
45924720
led_addr, phy_addr,
45934721
led_reg);
@@ -4599,29 +4727,28 @@ i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
45994727

46004728
if (time > 0 && interval > 0) {
46014729
for (i = 0; i < time * 1000; i += interval) {
4602-
status = i40e_read_phy_register(hw,
4603-
I40E_PHY_COM_REG_PAGE,
4604-
led_addr, phy_addr,
4605-
&led_reg);
4730+
status = i40e_read_phy_register_clause45(hw,
4731+
I40E_PHY_COM_REG_PAGE,
4732+
led_addr, phy_addr, &led_reg);
46064733
if (status)
46074734
goto restore_config;
46084735
if (led_reg & I40E_PHY_LED_MANUAL_ON)
46094736
led_reg = 0;
46104737
else
46114738
led_reg = I40E_PHY_LED_MANUAL_ON;
4612-
status = i40e_write_phy_register(hw,
4613-
I40E_PHY_COM_REG_PAGE,
4614-
led_addr, phy_addr,
4615-
led_reg);
4739+
status = i40e_write_phy_register_clause45(hw,
4740+
I40E_PHY_COM_REG_PAGE,
4741+
led_addr, phy_addr, led_reg);
46164742
if (status)
46174743
goto restore_config;
46184744
msleep(interval);
46194745
}
46204746
}
46214747

46224748
restore_config:
4623-
status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4624-
phy_addr, led_ctl);
4749+
status = i40e_write_phy_register_clause45(hw,
4750+
I40E_PHY_COM_REG_PAGE,
4751+
led_addr, phy_addr, led_ctl);
46254752

46264753
phy_blinking_end:
46274754
return status;
@@ -4652,8 +4779,10 @@ i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
46524779

46534780
for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
46544781
temp_addr++) {
4655-
status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4656-
temp_addr, phy_addr, &reg_val);
4782+
status = i40e_read_phy_register_clause45(hw,
4783+
I40E_PHY_COM_REG_PAGE,
4784+
temp_addr, phy_addr,
4785+
&reg_val);
46574786
if (status)
46584787
return status;
46594788
*val = reg_val;
@@ -4686,41 +4815,42 @@ i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
46864815
i = rd32(hw, I40E_PFGEN_PORTNUM);
46874816
port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
46884817
phy_addr = i40e_get_phy_address(hw, port_num);
4689-
4690-
status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4691-
phy_addr, &led_reg);
4818+
status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4819+
led_addr, phy_addr, &led_reg);
46924820
if (status)
46934821
return status;
46944822
led_ctl = led_reg;
46954823
if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
46964824
led_reg = 0;
4697-
status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4698-
led_addr, phy_addr, led_reg);
4825+
status = i40e_write_phy_register_clause45(hw,
4826+
I40E_PHY_COM_REG_PAGE,
4827+
led_addr, phy_addr,
4828+
led_reg);
46994829
if (status)
47004830
return status;
47014831
}
4702-
status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4703-
led_addr, phy_addr, &led_reg);
4832+
status = i40e_read_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4833+
led_addr, phy_addr, &led_reg);
47044834
if (status)
47054835
goto restore_config;
47064836
if (on)
47074837
led_reg = I40E_PHY_LED_MANUAL_ON;
47084838
else
47094839
led_reg = 0;
4710-
status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4711-
led_addr, phy_addr, led_reg);
4840+
status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4841+
led_addr, phy_addr, led_reg);
47124842
if (status)
47134843
goto restore_config;
47144844
if (mode & I40E_PHY_LED_MODE_ORIG) {
47154845
led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4716-
status = i40e_write_phy_register(hw,
4846+
status = i40e_write_phy_register_clause45(hw,
47174847
I40E_PHY_COM_REG_PAGE,
47184848
led_addr, phy_addr, led_ctl);
47194849
}
47204850
return status;
47214851
restore_config:
4722-
status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4723-
phy_addr, led_ctl);
4852+
status = i40e_write_phy_register_clause45(hw, I40E_PHY_COM_REG_PAGE,
4853+
led_addr, phy_addr, led_ctl);
47244854
return status;
47254855
}
47264856

0 commit comments

Comments
 (0)