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daviddaneyralfbaechle
daviddaney
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ralfbaechle
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MIPS: Add some instructions to uasm.
Follow on patches for eBPF JIT require these additional instructions: insn_bgtz, insn_blez, insn_break, insn_ddivu, insn_dmultu, insn_dsbh, insn_dshd, insn_dsllv, insn_dsra32, insn_dsrav, insn_dsrlv, insn_lbu, insn_movn, insn_movz, insn_multu, insn_nor, insn_sb, insn_sh, insn_slti, insn_dinsu, insn_lwu ... so, add them. Sort the insn_* enumeration values alphabetically. Signed-off-by: David Daney <david.daney@cavium.com> Cc: Alexei Starovoitov <ast@kernel.org> Cc: Daniel Borkmann <daniel@iogearbox.net> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: netdev@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16367/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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3 files changed

+96
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lines changed

‎arch/mips/include/asm/uasm.h

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,29 +72,41 @@ Ip_u1u2s3(_beq);
7272
Ip_u1u2s3(_beql);
7373
Ip_u1s2(_bgez);
7474
Ip_u1s2(_bgezl);
75+
Ip_u1s2(_bgtz);
76+
Ip_u1s2(_blez);
7577
Ip_u1s2(_bltz);
7678
Ip_u1s2(_bltzl);
7779
Ip_u1u2s3(_bne);
80+
Ip_u1(_break);
7881
Ip_u2s3u1(_cache);
7982
Ip_u1u2(_cfc1);
8083
Ip_u2u1(_cfcmsa);
8184
Ip_u1u2(_ctc1);
8285
Ip_u2u1(_ctcmsa);
8386
Ip_u2u1s3(_daddiu);
8487
Ip_u3u1u2(_daddu);
88+
Ip_u1u2(_ddivu);
8589
Ip_u1(_di);
8690
Ip_u2u1msbu3(_dins);
8791
Ip_u2u1msbu3(_dinsm);
92+
Ip_u2u1msbu3(_dinsu);
8893
Ip_u1u2(_divu);
8994
Ip_u1u2u3(_dmfc0);
9095
Ip_u1u2u3(_dmtc0);
96+
Ip_u1u2(_dmultu);
9197
Ip_u2u1u3(_drotr);
9298
Ip_u2u1u3(_drotr32);
99+
Ip_u2u1(_dsbh);
100+
Ip_u2u1(_dshd);
93101
Ip_u2u1u3(_dsll);
94102
Ip_u2u1u3(_dsll32);
103+
Ip_u3u2u1(_dsllv);
95104
Ip_u2u1u3(_dsra);
105+
Ip_u2u1u3(_dsra32);
106+
Ip_u3u2u1(_dsrav);
96107
Ip_u2u1u3(_dsrl);
97108
Ip_u2u1u3(_dsrl32);
109+
Ip_u3u2u1(_dsrlv);
98110
Ip_u3u1u2(_dsubu);
99111
Ip_0(_eret);
100112
Ip_u2u1msbu3(_ext);
@@ -104,6 +116,7 @@ Ip_u1(_jal);
104116
Ip_u2u1(_jalr);
105117
Ip_u1(_jr);
106118
Ip_u2s3u1(_lb);
119+
Ip_u2s3u1(_lbu);
107120
Ip_u2s3u1(_ld);
108121
Ip_u3u1u2(_ldx);
109122
Ip_u2s3u1(_lh);
@@ -112,27 +125,35 @@ Ip_u2s3u1(_ll);
112125
Ip_u2s3u1(_lld);
113126
Ip_u1s2(_lui);
114127
Ip_u2s3u1(_lw);
128+
Ip_u2s3u1(_lwu);
115129
Ip_u3u1u2(_lwx);
116130
Ip_u1u2u3(_mfc0);
117131
Ip_u1u2u3(_mfhc0);
118132
Ip_u1(_mfhi);
119133
Ip_u1(_mflo);
134+
Ip_u3u1u2(_movn);
135+
Ip_u3u1u2(_movz);
120136
Ip_u1u2u3(_mtc0);
121137
Ip_u1u2u3(_mthc0);
122138
Ip_u1(_mthi);
123139
Ip_u1(_mtlo);
124140
Ip_u3u1u2(_mul);
141+
Ip_u1u2(_multu);
142+
Ip_u3u1u2(_nor);
125143
Ip_u3u1u2(_or);
126144
Ip_u2u1u3(_ori);
127145
Ip_u2s3u1(_pref);
128146
Ip_0(_rfe);
129147
Ip_u2u1u3(_rotr);
148+
Ip_u2s3u1(_sb);
130149
Ip_u2s3u1(_sc);
131150
Ip_u2s3u1(_scd);
132151
Ip_u2s3u1(_sd);
152+
Ip_u2s3u1(_sh);
133153
Ip_u2u1u3(_sll);
134154
Ip_u3u2u1(_sllv);
135155
Ip_s3s1s2(_slt);
156+
Ip_u2u1s3(_slti);
136157
Ip_u2u1s3(_sltiu);
137158
Ip_u3u1u2(_sltu);
138159
Ip_u2u1u3(_sra);
@@ -248,6 +269,15 @@ static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
248269
uasm_i_dsrl32(p, a1, a2, a3 - 32);
249270
}
250271

272+
static inline void uasm_i_dsra_safe(u32 **p, unsigned int a1,
273+
unsigned int a2, unsigned int a3)
274+
{
275+
if (a3 < 32)
276+
uasm_i_dsra(p, a1, a2, a3);
277+
else
278+
uasm_i_dsra32(p, a1, a2, a3 - 32);
279+
}
280+
251281
/* Handle relocations. */
252282
struct uasm_reloc {
253283
u32 *addr;

‎arch/mips/mm/uasm-mips.c

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,9 +59,12 @@ static const struct insn const insn_table[insn_invalid] = {
5959
[insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
6060
[insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM},
6161
[insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM},
62+
[insn_bgtz] = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM},
63+
[insn_blez] = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM},
6264
[insn_bltz] = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM},
6365
[insn_bltzl] = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM},
6466
[insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM},
67+
[insn_break] = {M(spec_op, 0, 0, 0, 0, break_op), SCIMM},
6568
#ifndef CONFIG_CPU_MIPSR6
6669
[insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
6770
#else
@@ -73,19 +76,28 @@ static const struct insn const insn_table[insn_invalid] = {
7376
[insn_ctcmsa] = {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE},
7477
[insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
7578
[insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD},
79+
[insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT},
7680
[insn_di] = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT},
7781
[insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE},
7882
[insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE},
83+
[insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE},
7984
[insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT},
8085
[insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
8186
[insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
87+
[insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
8288
[insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
8389
[insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
90+
[insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD},
91+
[insn_dshd] = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD},
8492
[insn_dsll] = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE},
8593
[insn_dsll32] = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE},
94+
[insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD},
8695
[insn_dsra] = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE},
96+
[insn_dsra32] = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE},
97+
[insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD},
8798
[insn_dsrl] = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE},
8899
[insn_dsrl32] = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE},
100+
[insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD},
89101
[insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD},
90102
[insn_eret] = {M(cop0_op, cop_op, 0, 0, 0, eret_op), 0},
91103
[insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE},
@@ -99,6 +111,7 @@ static const struct insn const insn_table[insn_invalid] = {
99111
[insn_jr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS},
100112
#endif
101113
[insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
114+
[insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
102115
[insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
103116
[insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD},
104117
[insn_ldpte] = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD},
@@ -114,11 +127,14 @@ static const struct insn const insn_table[insn_invalid] = {
114127
#endif
115128
[insn_lui] = {M(lui_op, 0, 0, 0, 0, 0), RT | SIMM},
116129
[insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
130+
[insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
117131
[insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD},
118132
[insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
119133
[insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET},
120134
[insn_mfhi] = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD},
121135
[insn_mflo] = {M(spec_op, 0, 0, 0, 0, mflo_op), RD},
136+
[insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD},
137+
[insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD},
122138
[insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
123139
[insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET},
124140
[insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS},
@@ -128,6 +144,8 @@ static const struct insn const insn_table[insn_invalid] = {
128144
#else
129145
[insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD},
130146
#endif
147+
[insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT},
148+
[insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD},
131149
[insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD},
132150
[insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM},
133151
#ifndef CONFIG_CPU_MIPSR6
@@ -137,6 +155,7 @@ static const struct insn const insn_table[insn_invalid] = {
137155
#endif
138156
[insn_rfe] = {M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0},
139157
[insn_rotr] = {M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE},
158+
[insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
140159
#ifndef CONFIG_CPU_MIPSR6
141160
[insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
142161
[insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
@@ -145,9 +164,11 @@ static const struct insn const insn_table[insn_invalid] = {
145164
[insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9},
146165
#endif
147166
[insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
167+
[insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
148168
[insn_sll] = {M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE},
149169
[insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD},
150170
[insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD},
171+
[insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
151172
[insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM},
152173
[insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD},
153174
[insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE},

‎arch/mips/mm/uasm.c

Lines changed: 45 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -47,20 +47,24 @@ enum fields {
4747

4848
enum opcode {
4949
insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
50-
insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
51-
insn_bne, insn_cache, insn_cfc1, insn_cfcmsa, insn_ctc1, insn_ctcmsa,
52-
insn_daddiu, insn_daddu, insn_di, insn_dins, insn_dinsm, insn_divu,
53-
insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
54-
insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
55-
insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb,
56-
insn_ld, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw,
57-
insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi, insn_mflo, insn_mtc0,
58-
insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_or, insn_ori,
59-
insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll,
60-
insn_sllv, insn_slt, insn_sltiu, insn_sltu, insn_sra, insn_srl,
50+
insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bgtz, insn_blez,
51+
insn_bltz, insn_bltzl, insn_bne, insn_break, insn_cache, insn_cfc1,
52+
insn_cfcmsa, insn_ctc1, insn_ctcmsa, insn_daddiu, insn_daddu, insn_ddivu,
53+
insn_di, insn_dins, insn_dinsm, insn_dinsu, insn_divu, insn_dmfc0,
54+
insn_dmtc0, insn_dmultu, insn_drotr, insn_drotr32, insn_dsbh, insn_dshd,
55+
insn_dsll, insn_dsll32, insn_dsllv, insn_dsra, insn_dsra32, insn_dsrav,
56+
insn_dsrl, insn_dsrl32, insn_dsrlv, insn_dsubu, insn_eret, insn_ext,
57+
insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_lb, insn_lbu,
58+
insn_ld, insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu,
59+
insn_ll, insn_lld, insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0,
60+
insn_mfhc0, insn_mfhi, insn_mflo, insn_movn, insn_movz, insn_mtc0,
61+
insn_mthc0, insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_nor,
62+
insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb,
63+
insn_sc, insn_scd, insn_sd, insn_sh, insn_sll, insn_sllv,
64+
insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra, insn_srl,
6165
insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
6266
insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
63-
insn_xori, insn_yield, insn_lddir, insn_ldpte, insn_lhu,
67+
insn_xori, insn_yield,
6468
insn_invalid /* insn_invalid must be last */
6569
};
6670

@@ -214,6 +218,13 @@ Ip_u2u1msbu3(op) \
214218
} \
215219
UASM_EXPORT_SYMBOL(uasm_i##op);
216220

221+
#define I_u2u1msb32msb3(op) \
222+
Ip_u2u1msbu3(op) \
223+
{ \
224+
build_insn(buf, insn##op, b, a, c+d-33, c-32); \
225+
} \
226+
UASM_EXPORT_SYMBOL(uasm_i##op);
227+
217228
#define I_u2u1msbdu3(op) \
218229
Ip_u2u1msbu3(op) \
219230
{ \
@@ -264,25 +275,36 @@ I_u1u2s3(_beq)
264275
I_u1u2s3(_beql)
265276
I_u1s2(_bgez)
266277
I_u1s2(_bgezl)
278+
I_u1s2(_bgtz)
279+
I_u1s2(_blez)
267280
I_u1s2(_bltz)
268281
I_u1s2(_bltzl)
269282
I_u1u2s3(_bne)
283+
I_u1(_break)
270284
I_u2s3u1(_cache)
271285
I_u1u2(_cfc1)
272286
I_u2u1(_cfcmsa)
273287
I_u1u2(_ctc1)
274288
I_u2u1(_ctcmsa)
289+
I_u1u2(_ddivu)
275290
I_u1u2u3(_dmfc0)
276291
I_u1u2u3(_dmtc0)
292+
I_u1u2(_dmultu)
277293
I_u2u1s3(_daddiu)
278294
I_u3u1u2(_daddu)
279295
I_u1(_di);
280296
I_u1u2(_divu)
297+
I_u2u1(_dsbh);
298+
I_u2u1(_dshd);
281299
I_u2u1u3(_dsll)
282300
I_u2u1u3(_dsll32)
301+
I_u3u2u1(_dsllv)
283302
I_u2u1u3(_dsra)
303+
I_u2u1u3(_dsra32)
304+
I_u3u2u1(_dsrav)
284305
I_u2u1u3(_dsrl)
285306
I_u2u1u3(_dsrl32)
307+
I_u3u2u1(_dsrlv)
286308
I_u2u1u3(_drotr)
287309
I_u2u1u3(_drotr32)
288310
I_u3u1u2(_dsubu)
@@ -294,31 +316,40 @@ I_u1(_jal)
294316
I_u2u1(_jalr)
295317
I_u1(_jr)
296318
I_u2s3u1(_lb)
319+
I_u2s3u1(_lbu)
297320
I_u2s3u1(_ld)
298321
I_u2s3u1(_lh)
299322
I_u2s3u1(_lhu)
300323
I_u2s3u1(_ll)
301324
I_u2s3u1(_lld)
302325
I_u1s2(_lui)
303326
I_u2s3u1(_lw)
327+
I_u2s3u1(_lwu)
304328
I_u1u2u3(_mfc0)
305329
I_u1u2u3(_mfhc0)
330+
I_u3u1u2(_movn)
331+
I_u3u1u2(_movz)
306332
I_u1(_mfhi)
307333
I_u1(_mflo)
308334
I_u1u2u3(_mtc0)
309335
I_u1u2u3(_mthc0)
310336
I_u1(_mthi)
311337
I_u1(_mtlo)
312338
I_u3u1u2(_mul)
313-
I_u2u1u3(_ori)
339+
I_u1u2(_multu)
340+
I_u3u1u2(_nor)
314341
I_u3u1u2(_or)
342+
I_u2u1u3(_ori)
315343
I_0(_rfe)
344+
I_u2s3u1(_sb)
316345
I_u2s3u1(_sc)
317346
I_u2s3u1(_scd)
318347
I_u2s3u1(_sd)
348+
I_u2s3u1(_sh)
319349
I_u2u1u3(_sll)
320350
I_u3u2u1(_sllv)
321351
I_s3s1s2(_slt)
352+
I_u2u1s3(_slti)
322353
I_u2u1s3(_sltiu)
323354
I_u3u1u2(_sltu)
324355
I_u2u1u3(_sra)
@@ -339,6 +370,7 @@ I_u2u1u3(_xori)
339370
I_u2u1(_yield)
340371
I_u2u1msbu3(_dins);
341372
I_u2u1msb32u3(_dinsm);
373+
I_u2u1msb32msb3(_dinsu);
342374
I_u1(_syscall);
343375
I_u1u2s3(_bbit0);
344376
I_u1u2s3(_bbit1);

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