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69 | 69 | #define PHY_ID_VSC8234 0x000fc620
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70 | 70 | #define PHY_ID_VSC8244 0x000fc6c0
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71 | 71 | #define PHY_ID_VSC8514 0x00070670
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| 72 | +#define PHY_ID_VSC8572 0x000704d0 |
72 | 73 | #define PHY_ID_VSC8574 0x000704a0
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73 | 74 | #define PHY_ID_VSC8601 0x00070420
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74 | 75 | #define PHY_ID_VSC8662 0x00070660
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@@ -166,6 +167,7 @@ static int vsc82xx_config_intr(struct phy_device *phydev)
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166 | 167 | (phydev->drv->phy_id == PHY_ID_VSC8234 ||
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167 | 168 | phydev->drv->phy_id == PHY_ID_VSC8244 ||
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168 | 169 | phydev->drv->phy_id == PHY_ID_VSC8514 ||
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| 170 | + phydev->drv->phy_id == PHY_ID_VSC8572 || |
169 | 171 | phydev->drv->phy_id == PHY_ID_VSC8574 ||
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170 | 172 | phydev->drv->phy_id == PHY_ID_VSC8601) ?
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171 | 173 | MII_VSC8244_IMASK_MASK :
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@@ -290,6 +292,17 @@ static struct phy_driver vsc82xx_driver[] = {
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290 | 292 | .read_status = &genphy_read_status,
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291 | 293 | .ack_interrupt = &vsc824x_ack_interrupt,
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292 | 294 | .config_intr = &vsc82xx_config_intr,
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| 295 | +}, { |
| 296 | + .phy_id = PHY_ID_VSC8572, |
| 297 | + .name = "Vitesse VSC8572", |
| 298 | + .phy_id_mask = 0x000ffff0, |
| 299 | + .features = PHY_GBIT_FEATURES, |
| 300 | + .flags = PHY_HAS_INTERRUPT, |
| 301 | + .config_init = &vsc824x_config_init, |
| 302 | + .config_aneg = &vsc82x4_config_aneg, |
| 303 | + .read_status = &genphy_read_status, |
| 304 | + .ack_interrupt = &vsc824x_ack_interrupt, |
| 305 | + .config_intr = &vsc82xx_config_intr, |
293 | 306 | }, {
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294 | 307 | .phy_id = PHY_ID_VSC8574,
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295 | 308 | .name = "Vitesse VSC8574",
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@@ -355,6 +368,7 @@ static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
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355 | 368 | { PHY_ID_VSC8234, 0x000ffff0 },
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356 | 369 | { PHY_ID_VSC8244, 0x000fffc0 },
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357 | 370 | { PHY_ID_VSC8514, 0x000ffff0 },
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| 371 | + { PHY_ID_VSC8572, 0x000ffff0 }, |
358 | 372 | { PHY_ID_VSC8574, 0x000ffff0 },
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359 | 373 | { PHY_ID_VSC8662, 0x000ffff0 },
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360 | 374 | { PHY_ID_VSC8221, 0x000ffff0 },
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