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kirylH. Peter Anvin
kiryl
authored and
H. Peter Anvin
committed
x86, cpu: Detect more TLB configuration
The Intel Software Developer’s Manual covers few more TLB configurations exposed as CPUID 2 descriptors: 61H Instruction TLB: 4 KByte pages, fully associative, 48 entries 63H Data TLB: 1 GByte pages, 4-way set associative, 4 entries 76H Instruction TLB: 2M/4M pages, fully associative, 8 entries B5H Instruction TLB: 4KByte pages, 8-way set associative, 64 entries B6H Instruction TLB: 4KByte pages, 8-way set associative, 128 entries C1H Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries C2H DTLB DTLB: 2 MByte/$MByte pages, 4-way associative, 16 entries Let's detect them as well. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Link: http://lkml.kernel.org/r/1387801018-14499-1-git-send-email-kirill.shutemov@linux.intel.com Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
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-3
lines changed

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+31
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lines changed

‎arch/x86/include/asm/processor.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,7 @@ extern u16 __read_mostly tlb_lli_4m[NR_INFO];
7272
extern u16 __read_mostly tlb_lld_4k[NR_INFO];
7373
extern u16 __read_mostly tlb_lld_2m[NR_INFO];
7474
extern u16 __read_mostly tlb_lld_4m[NR_INFO];
75+
extern u16 __read_mostly tlb_lld_1g[NR_INFO];
7576
extern s8 __read_mostly tlb_flushall_shift;
7677

7778
/*

‎arch/x86/kernel/cpu/common.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -472,6 +472,7 @@ u16 __read_mostly tlb_lli_4m[NR_INFO];
472472
u16 __read_mostly tlb_lld_4k[NR_INFO];
473473
u16 __read_mostly tlb_lld_2m[NR_INFO];
474474
u16 __read_mostly tlb_lld_4m[NR_INFO];
475+
u16 __read_mostly tlb_lld_1g[NR_INFO];
475476

476477
/*
477478
* tlb_flushall_shift shows the balance point in replacing cr3 write
@@ -486,13 +487,13 @@ void cpu_detect_tlb(struct cpuinfo_x86 *c)
486487
if (this_cpu->c_detect_tlb)
487488
this_cpu->c_detect_tlb(c);
488489

489-
printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
490-
"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
490+
printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
491+
"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"
491492
"tlb_flushall_shift: %d\n",
492493
tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
493494
tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
494495
tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
495-
tlb_flushall_shift);
496+
tlb_lld_1g[ENTRIES], tlb_flushall_shift);
496497
}
497498

498499
void detect_ht(struct cpuinfo_x86 *c)

‎arch/x86/kernel/cpu/intel.c

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -506,6 +506,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
506506
#define TLB_DATA0_2M_4M 0x23
507507

508508
#define STLB_4K 0x41
509+
#define STLB_4K_2M 0x42
509510

510511
static const struct _tlb_table intel_tlb_table[] = {
511512
{ 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
@@ -526,13 +527,20 @@ static const struct _tlb_table intel_tlb_table[] = {
526527
{ 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
527528
{ 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
528529
{ 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
530+
{ 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
531+
{ 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
532+
{ 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
529533
{ 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
530534
{ 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
531535
{ 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
532536
{ 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
533537
{ 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
538+
{ 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" },
539+
{ 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" },
534540
{ 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
535541
{ 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
542+
{ 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
543+
{ 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
536544
{ 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
537545
{ 0x00, 0, 0 }
538546
};
@@ -558,6 +566,20 @@ static void intel_tlb_lookup(const unsigned char desc)
558566
if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
559567
tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
560568
break;
569+
case STLB_4K_2M:
570+
if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
571+
tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
572+
if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
573+
tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
574+
if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
575+
tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
576+
if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
577+
tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
578+
if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
579+
tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
580+
if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
581+
tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
582+
break;
561583
case TLB_INST_ALL:
562584
if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
563585
tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
@@ -603,6 +625,10 @@ static void intel_tlb_lookup(const unsigned char desc)
603625
if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
604626
tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
605627
break;
628+
case TLB_DATA_1G:
629+
if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
630+
tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
631+
break;
606632
}
607633
}
608634

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