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x86/intel_rdt: Use perf infrastructure for measurements
The success of a cache pseudo-locked region is measured using performance monitoring events that are programmed directly at the time the user requests a measurement. Modifying the performance event registers directly is not appropriate since it circumvents the in-kernel perf infrastructure that exists to manage these resources and provide resource arbitration to the performance monitoring hardware. The cache pseudo-locking measurements are modified to use the in-kernel perf infrastructure. Performance events are created and validated with the appropriate perf API. The performance counters are still read as directly as possible to avoid the additional cache hits. This is done safely by first ensuring with the perf API that the counters have been programmed correctly and only accessing the counters in an interrupt disabled section where they are not able to be moved. As part of the transition to the in-kernel perf infrastructure the L2 and L3 measurements are split into two separate measurements that can be triggered independently. This separation prevents additional cache misses incurred during the extra testing code used to decide if a L2 and/or L3 measurement should be made. Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: fenghua.yu@intel.com Cc: tony.luck@intel.com Cc: peterz@infradead.org Cc: acme@kernel.org Cc: gavin.hindman@intel.com Cc: jithu.joseph@intel.com Cc: dave.hansen@intel.com Cc: hpa@zytor.com Link: https://lkml.kernel.org/r/fc24e728b446404f42c78573c506e98cd0599873.1537468643.git.reinette.chatre@intel.com
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‎Documentation/x86/intel_rdt_ui.txt

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@@ -520,18 +520,24 @@ the pseudo-locked region:
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2) Cache hit and miss measurements using model specific precision counters if
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available. Depending on the levels of cache on the system the pseudo_lock_l2
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and pseudo_lock_l3 tracepoints are available.
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WARNING: triggering this measurement uses from two (for just L2
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measurements) to four (for L2 and L3 measurements) precision counters on
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the system, if any other measurements are in progress the counters and
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their corresponding event registers will be clobbered.
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When a pseudo-locked region is created a new debugfs directory is created for
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it in debugfs as /sys/kernel/debug/resctrl/<newdir>. A single
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write-only file, pseudo_lock_measure, is present in this directory. The
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measurement on the pseudo-locked region depends on the number, 1 or 2,
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written to this debugfs file. Since the measurements are recorded with the
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tracing infrastructure the relevant tracepoints need to be enabled before the
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measurement is triggered.
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measurement of the pseudo-locked region depends on the number written to this
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debugfs file:
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1 - writing "1" to the pseudo_lock_measure file will trigger the latency
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measurement captured in the pseudo_lock_mem_latency tracepoint. See
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example below.
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2 - writing "2" to the pseudo_lock_measure file will trigger the L2 cache
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residency (cache hits and misses) measurement captured in the
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pseudo_lock_l2 tracepoint. See example below.
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3 - writing "3" to the pseudo_lock_measure file will trigger the L3 cache
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residency (cache hits and misses) measurement captured in the
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pseudo_lock_l3 tracepoint.
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All measurements are recorded with the tracing infrastructure. This requires
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the relevant tracepoints to be enabled before the measurement is triggered.
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Example of latency debugging interface:
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In this example a pseudo-locked region named "newlock" was created. Here is

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