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Merge branch 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (21 commits) x86, mce: Fix compilation with !CONFIG_DEBUG_FS in mce-severity.c x86, mce: CE in last bank prevents panic by unknown MCE x86, mce: Fake panic support for MCE testing x86, mce: Move debugfs mce dir creating to mce.c x86, mce: Support specifying raise mode for software MCE injection x86, mce: Support specifying context for software mce injection x86, mce: fix reporting of Thermal Monitoring mechanism enabled x86, mce: remove never executed code x86, mce: add missing __cpuinit tags x86, mce: fix "mce" boot option handling for CONFIG_X86_NEW_MCE x86, mce: don't log boot MCEs on Pentium M (model == 13) CPUs x86: mce: Lower maximum number of banks to architecture limit x86: mce: macros to compute banks MSRs x86: mce: Move per bank data in a single datastructure x86: mce: Move code in mce.c x86: mce: Rename CONFIG_X86_NEW_MCE to CONFIG_X86_MCE x86: mce: Remove old i386 machine check code x86: mce: Update X86_MCE description in x86/Kconfig x86: mce: Make CONFIG_X86_ANCIENT_MCE dependent on CONFIG_X86_MCE x86, mce: use atomic_inc_return() instead of add by 1 ... Manually fixed up trivial conflicts: Documentation/feature-removal-schedule.txt arch/x86/kernel/cpu/mcheck/mce.c
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‎Documentation/feature-removal-schedule.txt

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@@ -428,16 +428,6 @@ Who: Johannes Berg <johannes@sipsolutions.net>
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----------------------------
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What: CONFIG_X86_OLD_MCE
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When: 2.6.32
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Why: Remove the old legacy 32bit machine check code. This has been
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superseded by the newer machine check code from the 64bit port,
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but the old version has been kept around for easier testing. Note this
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doesn't impact the old P5 and WinChip machine check handlers.
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Who: Andi Kleen <andi@firstfloor.org>
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----------------------------
440-
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What: lock_policy_rwsem_* and unlock_policy_rwsem_* will not be
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exported interface anymore.
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When: 2.6.33

‎arch/x86/Kconfig

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@@ -783,56 +783,32 @@ config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
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increased on these systems.
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config X86_MCE
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bool "Machine Check Exception"
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bool "Machine Check / overheating reporting"
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---help---
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Machine Check Exception support allows the processor to notify the
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kernel if it detects a problem (e.g. overheating, component failure).
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Machine Check support allows the processor to notify the
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kernel if it detects a problem (e.g. overheating, data corruption).
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The action the kernel takes depends on the severity of the problem,
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ranging from a warning message on the console, to halting the machine.
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Your processor must be a Pentium or newer to support this - check the
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flags in /proc/cpuinfo for mce. Note that some older Pentium systems
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have a design flaw which leads to false MCE events - hence MCE is
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disabled on all P5 processors, unless explicitly enabled with "mce"
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as a boot argument. Similarly, if MCE is built in and creates a
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problem on some new non-standard machine, you can boot with "nomce"
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to disable it. MCE support simply ignores non-MCE processors like
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the 386 and 486, so nearly everyone can say Y here.
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config X86_OLD_MCE
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depends on X86_32 && X86_MCE
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bool "Use legacy machine check code (will go away)"
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default n
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select X86_ANCIENT_MCE
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---help---
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Use the old i386 machine check code. This is merely intended for
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testing in a transition period. Try this if you run into any machine
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check related software problems, but report the problem to
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linux-kernel. When in doubt say no.
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config X86_NEW_MCE
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depends on X86_MCE
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bool
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default y if (!X86_OLD_MCE && X86_32) || X86_64
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ranging from warning messages to halting the machine.
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config X86_MCE_INTEL
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def_bool y
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prompt "Intel MCE features"
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depends on X86_NEW_MCE && X86_LOCAL_APIC
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depends on X86_MCE && X86_LOCAL_APIC
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---help---
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Additional support for intel specific MCE features such as
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the thermal monitor.
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config X86_MCE_AMD
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def_bool y
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prompt "AMD MCE features"
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depends on X86_NEW_MCE && X86_LOCAL_APIC
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depends on X86_MCE && X86_LOCAL_APIC
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---help---
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Additional support for AMD specific MCE features such as
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the DRAM Error Threshold.
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config X86_ANCIENT_MCE
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def_bool n
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depends on X86_32
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depends on X86_32 && X86_MCE
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prompt "Support for old Pentium 5 / WinChip machine checks"
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---help---
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Include support for machine check handling on old Pentium 5 or WinChip
@@ -845,36 +821,16 @@ config X86_MCE_THRESHOLD
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default y
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config X86_MCE_INJECT
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depends on X86_NEW_MCE
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depends on X86_MCE
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tristate "Machine check injector support"
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---help---
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Provide support for injecting machine checks for testing purposes.
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If you don't know what a machine check is and you don't do kernel
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QA it is safe to say n.
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config X86_MCE_NONFATAL
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tristate "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4"
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depends on X86_OLD_MCE
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---help---
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Enabling this feature starts a timer that triggers every 5 seconds which
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will look at the machine check registers to see if anything happened.
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Non-fatal problems automatically get corrected (but still logged).
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Disable this if you don't want to see these messages.
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Seeing the messages this option prints out may be indicative of dying
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or out-of-spec (ie, overclocked) hardware.
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This option only does something on certain CPUs.
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(AMD Athlon/Duron and Intel Pentium 4)
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config X86_MCE_P4THERMAL
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bool "check for P4 thermal throttling interrupt."
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depends on X86_OLD_MCE && X86_MCE && (X86_UP_APIC || SMP)
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---help---
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Enabling this feature will cause a message to be printed when the P4
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enters thermal throttling.
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config X86_THERMAL_VECTOR
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def_bool y
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depends on X86_MCE_P4THERMAL || X86_MCE_INTEL
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depends on X86_MCE_INTEL
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config VM86
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bool "Enable VM86 support" if EMBEDDED

‎arch/x86/include/asm/entry_arch.h

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@@ -61,7 +61,7 @@ BUILD_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)
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BUILD_INTERRUPT(threshold_interrupt,THRESHOLD_APIC_VECTOR)
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#endif
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64-
#ifdef CONFIG_X86_NEW_MCE
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#ifdef CONFIG_X86_MCE
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BUILD_INTERRUPT(mce_self_interrupt,MCE_SELF_VECTOR)
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#endif
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‎arch/x86/include/asm/mce.h

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@@ -9,7 +9,7 @@
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*/
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#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
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#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
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#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
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#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
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#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
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#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
@@ -38,6 +38,14 @@
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#define MCM_ADDR_MEM 3 /* memory address */
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#define MCM_ADDR_GENERIC 7 /* generic */
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#define MCJ_CTX_MASK 3
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#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
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#define MCJ_CTX_RANDOM 0 /* inject context: random */
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#define MCJ_CTX_PROCESS 1 /* inject context: process */
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#define MCJ_CTX_IRQ 2 /* inject context: IRQ */
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#define MCJ_NMI_BROADCAST 4 /* do NMI broadcasting */
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#define MCJ_EXCEPTION 8 /* raise as exception */
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/* Fields are zero when not available */
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struct mce {
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__u64 status;
@@ -48,8 +56,8 @@ struct mce {
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__u64 tsc; /* cpu time stamp counter */
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__u64 time; /* wall time_t when error was detected */
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__u8 cpuvendor; /* cpu vendor as encoded in system.h */
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__u8 pad1;
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__u16 pad2;
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__u8 inject_flags; /* software inject flags */
60+
__u16 pad;
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__u32 cpuid; /* CPUID 1 EAX */
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__u8 cs; /* code segment */
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__u8 bank; /* machine check bank */
@@ -115,13 +123,6 @@ void mcheck_init(struct cpuinfo_x86 *c);
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static inline void mcheck_init(struct cpuinfo_x86 *c) {}
116124
#endif
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118-
#ifdef CONFIG_X86_OLD_MCE
119-
extern int nr_mce_banks;
120-
void amd_mcheck_init(struct cpuinfo_x86 *c);
121-
void intel_p4_mcheck_init(struct cpuinfo_x86 *c);
122-
void intel_p6_mcheck_init(struct cpuinfo_x86 *c);
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#endif
124-
125126
#ifdef CONFIG_X86_ANCIENT_MCE
126127
void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
127128
void winchip_mcheck_init(struct cpuinfo_x86 *c);
@@ -137,10 +138,11 @@ void mce_log(struct mce *m);
137138
DECLARE_PER_CPU(struct sys_device, mce_dev);
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139140
/*
140-
* To support more than 128 would need to escape the predefined
141-
* Linux defined extended banks first.
141+
* Maximum banks number.
142+
* This is the limit of the current register layout on
143+
* Intel CPUs.
142144
*/
143-
#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)
145+
#define MAX_NR_BANKS 32
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145147
#ifdef CONFIG_X86_MCE_INTEL
146148
extern int mce_cmci_disabled;
@@ -208,11 +210,7 @@ extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
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209211
void intel_init_thermal(struct cpuinfo_x86 *c);
210212

211-
#ifdef CONFIG_X86_NEW_MCE
212213
void mce_log_therm_throt_event(__u64 status);
213-
#else
214-
static inline void mce_log_therm_throt_event(__u64 status) {}
215-
#endif
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217215
#endif /* __KERNEL__ */
218216
#endif /* _ASM_X86_MCE_H */

‎arch/x86/include/asm/msr-index.h

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@@ -81,8 +81,15 @@
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#define MSR_IA32_MC0_ADDR 0x00000402
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#define MSR_IA32_MC0_MISC 0x00000403
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84+
#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
85+
#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
86+
#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
87+
#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
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8489
/* These are consecutive and not in the normal 4er MCE bank block */
8590
#define MSR_IA32_MC0_CTL2 0x00000280
91+
#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
92+
8693
#define CMCI_EN (1ULL << 30)
8794
#define CMCI_THRESHOLD_MASK 0xffffULL
8895

@@ -215,6 +222,10 @@
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216223
#define THERM_STATUS_PROCHOT (1 << 0)
217224

225+
#define MSR_THERM2_CTL 0x0000019d
226+
227+
#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
228+
218229
#define MSR_IA32_MISC_ENABLE 0x000001a0
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/* MISC_ENABLE bits: architectural */

‎arch/x86/kernel/apic/nmi.c

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@@ -66,7 +66,7 @@ static inline unsigned int get_nmi_count(int cpu)
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static inline int mce_in_progress(void)
6868
{
69-
#if defined(CONFIG_X86_NEW_MCE)
69+
#if defined(CONFIG_X86_MCE)
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return atomic_read(&mce_entry) > 0;
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#endif
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return 0;

‎arch/x86/kernel/cpu/mcheck/Makefile

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1-
obj-y = mce.o
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obj-y = mce.o mce-severity.o
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3-
obj-$(CONFIG_X86_NEW_MCE) += mce-severity.o
4-
obj-$(CONFIG_X86_OLD_MCE) += k7.o p4.o p6.o
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obj-$(CONFIG_X86_ANCIENT_MCE) += winchip.o p5.o
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obj-$(CONFIG_X86_MCE_INTEL) += mce_intel.o
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obj-$(CONFIG_X86_MCE_AMD) += mce_amd.o
8-
obj-$(CONFIG_X86_MCE_NONFATAL) += non-fatal.o
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obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o
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obj-$(CONFIG_X86_MCE_INJECT) += mce-inject.o
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‎arch/x86/kernel/cpu/mcheck/k7.c

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