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atorgueKAGA-KOKO
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drivers/irqchip: Add STM32 external interrupts support
The STM32 external interrupt controller consists of edge detectors that generate interrupts requests or wake-up events. Each line can be independently configured as interrupt or wake-up source, and triggers either on rising, falling or both edges. Each line can also be masked independently. Originally-from: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: arnd@arndb.de Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: bruherrera@gmail.com Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: lee.jones@linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1474387259-18926-3-git-send-email-alexandre.torgue@st.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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‎drivers/irqchip/Kconfig

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@@ -265,3 +265,7 @@ config EZNPS_GIC
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select IRQ_DOMAIN
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help
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Support the EZchip NPS400 global interrupt controller
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config STM32_EXTI
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bool
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select IRQ_DOMAIN

‎drivers/irqchip/Makefile

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@@ -71,3 +71,4 @@ obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
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obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
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obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
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obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o
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obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o

‎drivers/irqchip/irq-stm32-exti.c

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/*
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* Copyright (C) Maxime Coquelin 2015
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* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define EXTI_IMR 0x0
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#define EXTI_EMR 0x4
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#define EXTI_RTSR 0x8
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#define EXTI_FTSR 0xc
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#define EXTI_SWIER 0x10
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#define EXTI_PR 0x14
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static void stm32_irq_handler(struct irq_desc *desc)
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{
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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struct irq_chip_generic *gc = domain->gc->gc[0];
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned long pending;
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int n;
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chained_irq_enter(chip, desc);
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while ((pending = irq_reg_readl(gc, EXTI_PR))) {
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for_each_set_bit(n, &pending, BITS_PER_LONG) {
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generic_handle_irq(irq_find_mapping(domain, n));
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irq_reg_writel(gc, BIT(n), EXTI_PR);
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}
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}
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chained_irq_exit(chip, desc);
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}
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static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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int pin = data->hwirq;
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u32 rtsr, ftsr;
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irq_gc_lock(gc);
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rtsr = irq_reg_readl(gc, EXTI_RTSR);
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ftsr = irq_reg_readl(gc, EXTI_FTSR);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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rtsr |= BIT(pin);
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ftsr &= ~BIT(pin);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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rtsr &= ~BIT(pin);
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ftsr |= BIT(pin);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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rtsr |= BIT(pin);
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ftsr |= BIT(pin);
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break;
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default:
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irq_gc_unlock(gc);
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return -EINVAL;
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}
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irq_reg_writel(gc, rtsr, EXTI_RTSR);
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irq_reg_writel(gc, ftsr, EXTI_FTSR);
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irq_gc_unlock(gc);
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return 0;
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}
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static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
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int pin = data->hwirq;
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u32 emr;
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irq_gc_lock(gc);
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emr = irq_reg_readl(gc, EXTI_EMR);
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if (on)
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emr |= BIT(pin);
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else
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emr &= ~BIT(pin);
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irq_reg_writel(gc, emr, EXTI_EMR);
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irq_gc_unlock(gc);
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return 0;
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}
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static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_chip_generic *gc = d->gc->gc[0];
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struct irq_fwspec *fwspec = data;
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irq_hw_number_t hwirq;
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hwirq = fwspec->param[0];
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irq_map_generic_chip(d, virq, hwirq);
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irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
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handle_simple_irq, NULL, NULL);
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return 0;
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}
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static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *data = irq_domain_get_irq_data(d, virq);
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irq_domain_reset_irq_data(data);
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}
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struct irq_domain_ops irq_exti_domain_ops = {
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.map = irq_map_generic_chip,
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.xlate = irq_domain_xlate_onetwocell,
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.alloc = stm32_exti_alloc,
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.free = stm32_exti_free,
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};
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static int __init stm32_exti_init(struct device_node *node,
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struct device_node *parent)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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int nr_irqs, nr_exti, ret, i;
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struct irq_chip_generic *gc;
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struct irq_domain *domain;
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void *base;
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("%s: Unable to map registers\n", node->full_name);
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return -ENOMEM;
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}
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/* Determine number of irqs supported */
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writel_relaxed(~0UL, base + EXTI_RTSR);
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nr_exti = fls(readl_relaxed(base + EXTI_RTSR));
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writel_relaxed(0, base + EXTI_RTSR);
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pr_info("%s: %d External IRQs detected\n", node->full_name, nr_exti);
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domain = irq_domain_add_linear(node, nr_exti,
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&irq_exti_domain_ops, NULL);
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if (!domain) {
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pr_err("%s: Could not register interrupt domain.\n",
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node->name);
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ret = -ENOMEM;
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goto out_unmap;
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}
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ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti",
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handle_edge_irq, clr, 0, 0);
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if (ret) {
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pr_err("%s: Could not allocate generic interrupt chip.\n",
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node->full_name);
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goto out_free_domain;
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}
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gc = domain->gc->gc[0];
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gc->reg_base = base;
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gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
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gc->chip_types->chip.name = gc->chip_types[0].chip.name;
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gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
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gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
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gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
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gc->chip_types->regs.ack = EXTI_PR;
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gc->chip_types->regs.mask = EXTI_IMR;
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gc->chip_types->handler = handle_edge_irq;
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nr_irqs = of_irq_count(node);
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for (i = 0; i < nr_irqs; i++) {
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unsigned int irq = irq_of_parse_and_map(node, i);
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irq_set_handler_data(irq, domain);
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irq_set_chained_handler(irq, stm32_irq_handler);
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}
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return 0;
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out_free_domain:
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irq_domain_remove(domain);
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out_unmap:
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iounmap(base);
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return ret;
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}
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IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init);

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