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Tariq Toukandavem330
Tariq Toukan
authored and
davem330
committed
net/mlx5: Fix mlx5 ifc cmd_hca_cap bad offsets
All reserved fields after early_vf_enable are off by 1, since early_vf_enable was not explicitly declared as array of size 1. Reserved field before cqe_zip had a wrong size, it should be 0x80 + 0x3f. Fixes: b084444 ("net/mlx5_core: Introduce access function to read internal timer ") Fixes: b4ff3a3 ("net/mlx5: Use offset based reserved field names in the IFC header file") Signed-off-by: Tariq Toukan <tariqt@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Matan Barak <matanb@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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‎include/linux/mlx5/mlx5_ifc.h

Lines changed: 55 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -750,21 +750,21 @@ struct mlx5_ifc_cmd_hca_cap_bits {
750750
u8 ets[0x1];
751751
u8 nic_flow_table[0x1];
752752
u8 eswitch_flow_table[0x1];
753-
u8 early_vf_enable;
754-
u8 reserved_at_1a8[0x2];
753+
u8 early_vf_enable[0x1];
754+
u8 reserved_at_1a9[0x2];
755755
u8 local_ca_ack_delay[0x5];
756756
u8 reserved_at_1af[0x6];
757757
u8 port_type[0x2];
758758
u8 num_ports[0x8];
759759

760-
u8 reserved_at_1bf[0x3];
760+
u8 reserved_at_1c0[0x3];
761761
u8 log_max_msg[0x5];
762-
u8 reserved_at_1c7[0x4];
762+
u8 reserved_at_1c8[0x4];
763763
u8 max_tc[0x4];
764-
u8 reserved_at_1cf[0x6];
764+
u8 reserved_at_1d0[0x6];
765765
u8 rol_s[0x1];
766766
u8 rol_g[0x1];
767-
u8 reserved_at_1d7[0x1];
767+
u8 reserved_at_1d8[0x1];
768768
u8 wol_s[0x1];
769769
u8 wol_g[0x1];
770770
u8 wol_a[0x1];
@@ -774,47 +774,47 @@ struct mlx5_ifc_cmd_hca_cap_bits {
774774
u8 wol_p[0x1];
775775

776776
u8 stat_rate_support[0x10];
777-
u8 reserved_at_1ef[0xc];
777+
u8 reserved_at_1f0[0xc];
778778
u8 cqe_version[0x4];
779779

780780
u8 compact_address_vector[0x1];
781781
u8 reserved_at_200[0x3];
782782
u8 ipoib_basic_offloads[0x1];
783-
u8 reserved_at_204[0xa];
783+
u8 reserved_at_205[0xa];
784784
u8 drain_sigerr[0x1];
785785
u8 cmdif_checksum[0x2];
786786
u8 sigerr_cqe[0x1];
787-
u8 reserved_at_212[0x1];
787+
u8 reserved_at_213[0x1];
788788
u8 wq_signature[0x1];
789789
u8 sctr_data_cqe[0x1];
790-
u8 reserved_at_215[0x1];
790+
u8 reserved_at_216[0x1];
791791
u8 sho[0x1];
792792
u8 tph[0x1];
793793
u8 rf[0x1];
794794
u8 dct[0x1];
795-
u8 reserved_at_21a[0x1];
795+
u8 reserved_at_21b[0x1];
796796
u8 eth_net_offloads[0x1];
797797
u8 roce[0x1];
798798
u8 atomic[0x1];
799-
u8 reserved_at_21e[0x1];
799+
u8 reserved_at_21f[0x1];
800800

801801
u8 cq_oi[0x1];
802802
u8 cq_resize[0x1];
803803
u8 cq_moderation[0x1];
804-
u8 reserved_at_222[0x3];
804+
u8 reserved_at_223[0x3];
805805
u8 cq_eq_remap[0x1];
806806
u8 pg[0x1];
807807
u8 block_lb_mc[0x1];
808-
u8 reserved_at_228[0x1];
808+
u8 reserved_at_229[0x1];
809809
u8 scqe_break_moderation[0x1];
810810
u8 reserved_at_22a[0x1];
811811
u8 cd[0x1];
812-
u8 reserved_at_22c[0x1];
812+
u8 reserved_at_22d[0x1];
813813
u8 apm[0x1];
814814
u8 vector_calc[0x1];
815815
u8 reserved_at_22f[0x1];
816816
u8 imaicl[0x1];
817-
u8 reserved_at_231[0x4];
817+
u8 reserved_at_232[0x4];
818818
u8 qkv[0x1];
819819
u8 pkv[0x1];
820820
u8 set_deth_sqpn[0x1];
@@ -824,98 +824,101 @@ struct mlx5_ifc_cmd_hca_cap_bits {
824824
u8 uc[0x1];
825825
u8 rc[0x1];
826826

827-
u8 reserved_at_23f[0xa];
827+
u8 reserved_at_240[0xa];
828828
u8 uar_sz[0x6];
829-
u8 reserved_at_24f[0x8];
829+
u8 reserved_at_250[0x8];
830830
u8 log_pg_sz[0x8];
831831

832832
u8 bf[0x1];
833-
u8 reserved_at_260[0x1];
833+
u8 reserved_at_261[0x1];
834834
u8 pad_tx_eth_packet[0x1];
835-
u8 reserved_at_262[0x8];
835+
u8 reserved_at_263[0x8];
836836
u8 log_bf_reg_size[0x5];
837-
u8 reserved_at_26f[0x10];
837+
u8 reserved_at_270[0x10];
838838

839-
u8 reserved_at_27f[0x10];
839+
u8 reserved_at_280[0x10];
840840
u8 max_wqe_sz_sq[0x10];
841841

842-
u8 reserved_at_29f[0x10];
842+
u8 reserved_at_2a0[0x10];
843843
u8 max_wqe_sz_rq[0x10];
844844

845-
u8 reserved_at_2bf[0x10];
845+
u8 reserved_at_2c0[0x10];
846846
u8 max_wqe_sz_sq_dc[0x10];
847847

848-
u8 reserved_at_2df[0x7];
848+
u8 reserved_at_2e0[0x7];
849849
u8 max_qp_mcg[0x19];
850850

851-
u8 reserved_at_2ff[0x18];
851+
u8 reserved_at_300[0x18];
852852
u8 log_max_mcg[0x8];
853853

854-
u8 reserved_at_31f[0x3];
854+
u8 reserved_at_320[0x3];
855855
u8 log_max_transport_domain[0x5];
856-
u8 reserved_at_327[0x3];
856+
u8 reserved_at_328[0x3];
857857
u8 log_max_pd[0x5];
858-
u8 reserved_at_32f[0xb];
858+
u8 reserved_at_330[0xb];
859859
u8 log_max_xrcd[0x5];
860860

861-
u8 reserved_at_33f[0x20];
861+
u8 reserved_at_340[0x20];
862862

863-
u8 reserved_at_35f[0x3];
863+
u8 reserved_at_360[0x3];
864864
u8 log_max_rq[0x5];
865-
u8 reserved_at_367[0x3];
865+
u8 reserved_at_368[0x3];
866866
u8 log_max_sq[0x5];
867-
u8 reserved_at_36f[0x3];
867+
u8 reserved_at_370[0x3];
868868
u8 log_max_tir[0x5];
869-
u8 reserved_at_377[0x3];
869+
u8 reserved_at_378[0x3];
870870
u8 log_max_tis[0x5];
871871

872872
u8 basic_cyclic_rcv_wqe[0x1];
873-
u8 reserved_at_380[0x2];
873+
u8 reserved_at_381[0x2];
874874
u8 log_max_rmp[0x5];
875-
u8 reserved_at_387[0x3];
875+
u8 reserved_at_388[0x3];
876876
u8 log_max_rqt[0x5];
877-
u8 reserved_at_38f[0x3];
877+
u8 reserved_at_390[0x3];
878878
u8 log_max_rqt_size[0x5];
879-
u8 reserved_at_397[0x3];
879+
u8 reserved_at_398[0x3];
880880
u8 log_max_tis_per_sq[0x5];
881881

882-
u8 reserved_at_39f[0x3];
882+
u8 reserved_at_3a0[0x3];
883883
u8 log_max_stride_sz_rq[0x5];
884-
u8 reserved_at_3a7[0x3];
884+
u8 reserved_at_3a8[0x3];
885885
u8 log_min_stride_sz_rq[0x5];
886-
u8 reserved_at_3af[0x3];
886+
u8 reserved_at_3b0[0x3];
887887
u8 log_max_stride_sz_sq[0x5];
888-
u8 reserved_at_3b7[0x3];
888+
u8 reserved_at_3b8[0x3];
889889
u8 log_min_stride_sz_sq[0x5];
890890

891-
u8 reserved_at_3bf[0x1b];
891+
u8 reserved_at_3c0[0x1b];
892892
u8 log_max_wq_sz[0x5];
893893

894894
u8 nic_vport_change_event[0x1];
895-
u8 reserved_at_3e0[0xa];
895+
u8 reserved_at_3e1[0xa];
896896
u8 log_max_vlan_list[0x5];
897-
u8 reserved_at_3ef[0x3];
897+
u8 reserved_at_3f0[0x3];
898898
u8 log_max_current_mc_list[0x5];
899-
u8 reserved_at_3f7[0x3];
899+
u8 reserved_at_3f8[0x3];
900900
u8 log_max_current_uc_list[0x5];
901901

902-
u8 reserved_at_3ff[0x80];
902+
u8 reserved_at_400[0x80];
903903

904-
u8 reserved_at_47f[0x3];
904+
u8 reserved_at_480[0x3];
905905
u8 log_max_l2_table[0x5];
906-
u8 reserved_at_487[0x8];
906+
u8 reserved_at_488[0x8];
907907
u8 log_uar_page_sz[0x10];
908908

909-
u8 reserved_at_49f[0x20];
909+
u8 reserved_at_4a0[0x20];
910910
u8 device_frequency_mhz[0x20];
911911
u8 device_frequency_khz[0x20];
912-
u8 reserved_at_4ff[0x5f];
912+
913+
u8 reserved_at_500[0x80];
914+
915+
u8 reserved_at_580[0x3f];
913916
u8 cqe_zip[0x1];
914917

915918
u8 cqe_zip_timeout[0x10];
916919
u8 cqe_zip_max_num[0x10];
917920

918-
u8 reserved_at_57f[0x220];
921+
u8 reserved_at_5e0[0x220];
919922
};
920923

921924
enum mlx5_flow_destination_type {

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